1*10465441SEvalZero /*
2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team
3*10465441SEvalZero *
4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0
5*10465441SEvalZero *
6*10465441SEvalZero * Change Logs:
7*10465441SEvalZero * Date Author Notes
8*10465441SEvalZero * 2008-04-25 Yi.qiu first version
9*10465441SEvalZero */
10*10465441SEvalZero
11*10465441SEvalZero #include <rtthread.h>
12*10465441SEvalZero #include "s3c24x0.h"
13*10465441SEvalZero
14*10465441SEvalZero #define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz
15*10465441SEvalZero
16*10465441SEvalZero #if CONFIG_SYS_CLK_FREQ == 12000000
17*10465441SEvalZero /* MPLL=2*12*100/6=400MHz */
18*10465441SEvalZero #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */
19*10465441SEvalZero #define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */
20*10465441SEvalZero #define MPL_SDIV 0 /* s=MPL_SDIV=0 */
21*10465441SEvalZero /* UPLL=12*64/8=96MHz */
22*10465441SEvalZero #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */
23*10465441SEvalZero #define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */
24*10465441SEvalZero #define UPL_SDIV 1 /* s=UPL_SDIV=1 */
25*10465441SEvalZero /* System clock divider FCLK:HCLK:PCLK=1:4:8 */
26*10465441SEvalZero #define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */
27*10465441SEvalZero #define HDIVN 0x2 /* HCLK = FCLK / 4 */
28*10465441SEvalZero #define PDIVN 0x1 /* PCLK = HCLK / 2 */
29*10465441SEvalZero #endif
30*10465441SEvalZero
31*10465441SEvalZero rt_uint32_t PCLK;
32*10465441SEvalZero rt_uint32_t FCLK;
33*10465441SEvalZero rt_uint32_t HCLK;
34*10465441SEvalZero rt_uint32_t UCLK;
35*10465441SEvalZero
rt_hw_get_clock(void)36*10465441SEvalZero void rt_hw_get_clock(void)
37*10465441SEvalZero {
38*10465441SEvalZero rt_uint32_t val;
39*10465441SEvalZero rt_uint8_t m, p, s;
40*10465441SEvalZero
41*10465441SEvalZero val = MPLLCON;
42*10465441SEvalZero m = (val>>12)&0xff;
43*10465441SEvalZero p = (val>>4)&0x3f;
44*10465441SEvalZero s = val&3;
45*10465441SEvalZero
46*10465441SEvalZero FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100;
47*10465441SEvalZero
48*10465441SEvalZero val = CLKDIVN;
49*10465441SEvalZero m = (val>>1)&3;
50*10465441SEvalZero p = val&1;
51*10465441SEvalZero
52*10465441SEvalZero switch (m) {
53*10465441SEvalZero case 0:
54*10465441SEvalZero HCLK = FCLK;
55*10465441SEvalZero break;
56*10465441SEvalZero case 1:
57*10465441SEvalZero HCLK = FCLK>>1;
58*10465441SEvalZero break;
59*10465441SEvalZero case 2:
60*10465441SEvalZero if(s&2)
61*10465441SEvalZero HCLK = FCLK>>3;
62*10465441SEvalZero else
63*10465441SEvalZero HCLK = FCLK>>2;
64*10465441SEvalZero break;
65*10465441SEvalZero case 3:
66*10465441SEvalZero if(s&1)
67*10465441SEvalZero HCLK = FCLK/6;
68*10465441SEvalZero else
69*10465441SEvalZero HCLK = FCLK/3;
70*10465441SEvalZero break;
71*10465441SEvalZero }
72*10465441SEvalZero
73*10465441SEvalZero if(p)
74*10465441SEvalZero PCLK = HCLK>>1;
75*10465441SEvalZero else
76*10465441SEvalZero PCLK = HCLK;
77*10465441SEvalZero }
78*10465441SEvalZero
rt_hw_set_mpll_clock(rt_uint8_t sdiv,rt_uint8_t pdiv,rt_uint8_t mdiv)79*10465441SEvalZero void rt_hw_set_mpll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
80*10465441SEvalZero {
81*10465441SEvalZero MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12);
82*10465441SEvalZero }
83*10465441SEvalZero
rt_hw_set_upll_clock(rt_uint8_t sdiv,rt_uint8_t pdiv,rt_uint8_t mdiv)84*10465441SEvalZero void rt_hw_set_upll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv)
85*10465441SEvalZero {
86*10465441SEvalZero UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv;
87*10465441SEvalZero }
88*10465441SEvalZero
rt_hw_set_divider(rt_uint8_t hdivn,rt_uint8_t pdivn)89*10465441SEvalZero void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn)
90*10465441SEvalZero {
91*10465441SEvalZero CLKDIVN = (hdivn<<1) | pdivn;
92*10465441SEvalZero }
93*10465441SEvalZero
94*10465441SEvalZero /**
95*10465441SEvalZero * @brief System Clock Configuration
96*10465441SEvalZero */
rt_hw_clock_init(void)97*10465441SEvalZero void rt_hw_clock_init(void)
98*10465441SEvalZero {
99*10465441SEvalZero LOCKTIME = 0xFFFFFFFF;
100*10465441SEvalZero rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV);
101*10465441SEvalZero rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV);
102*10465441SEvalZero rt_hw_set_divider(HDIVN, PDIVN);
103*10465441SEvalZero }
104*10465441SEvalZero
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