1;/*****************************************************************************/ 2;/* STARTUP.S: Startup file for Philips LPC2000 */ 3;/*****************************************************************************/ 4;/* <<< Use Configuration Wizard in Context Menu >>> */ 5;/*****************************************************************************/ 6;/* This file is part of the uVision/ARM development tools. */ 7;/* Copyright (c) 2005-2007 Keil Software. All rights reserved. */ 8;/* This software may only be used under the terms of a valid, current, */ 9;/* end user licence from KEIL for a compatible version of KEIL software */ 10;/* development tools. Nothing else gives you the right to use this software. */ 11;/*****************************************************************************/ 12 13 14;/* 15; * The STARTUP.S code is executed after CPU Reset. This file may be 16; * translated with the following SET symbols. In uVision these SET 17; * symbols are entered under Options - ASM - Define. 18; * 19; * REMAP: when set the startup code initializes the register MEMMAP 20; * which overwrites the settings of the CPU configuration pins. The 21; * startup and interrupt vectors are remapped from: 22; * 0x00000000 default setting (not remapped) 23; * 0x80000000 when EXTMEM_MODE is used 24; * 0x40000000 when RAM_MODE is used 25; * 26; * EXTMEM_MODE: when set the device is configured for code execution 27; * from external memory starting at address 0x80000000. 28; * 29; * RAM_MODE: when set the device is configured for code execution 30; * from on-chip RAM starting at address 0x40000000. 31; * 32; * EXTERNAL_MODE: when set the PIN2SEL values are written that enable 33; * the external BUS at startup. 34; */ 35 36 37; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs 38 39Mode_USR EQU 0x10 40Mode_FIQ EQU 0x11 41Mode_IRQ EQU 0x12 42Mode_SVC EQU 0x13 43Mode_ABT EQU 0x17 44Mode_UND EQU 0x1B 45Mode_SYS EQU 0x1F 46 47I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled 48F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled 49 50 51;// <h> Stack Configuration (Stack Sizes in Bytes) 52;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8> 53;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8> 54;// <o2> Abort Mode <0x0-0xFFFFFFFF:8> 55;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8> 56;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8> 57;// <o5> User/System Mode <0x0-0xFFFFFFFF:8> 58;// </h> 59 60UND_Stack_Size EQU 0x00000000 61SVC_Stack_Size EQU 0x00000100 62ABT_Stack_Size EQU 0x00000000 63FIQ_Stack_Size EQU 0x00000000 64IRQ_Stack_Size EQU 0x00000100 65USR_Stack_Size EQU 0x00000100 66 67ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ 68 FIQ_Stack_Size + IRQ_Stack_Size) 69 70 AREA STACK, NOINIT, READWRITE, ALIGN=3 71 72Stack_Mem SPACE USR_Stack_Size 73__initial_sp SPACE ISR_Stack_Size 74 75Stack_Top 76 77 78;// <h> Heap Configuration 79;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF> 80;// </h> 81 82Heap_Size EQU 0x00000000 83 84 AREA HEAP, NOINIT, READWRITE, ALIGN=3 85__heap_base 86Heap_Mem SPACE Heap_Size 87__heap_limit 88 89 90; VPBDIV definitions 91VPBDIV EQU 0xE01FC100 ; VPBDIV Address 92 93;// <e> VPBDIV Setup 94;// <i> Peripheral Bus Clock Rate 95;// <o1.0..1> VPBDIV: VPB Clock 96;// <0=> VPB Clock = CPU Clock / 4 97;// <1=> VPB Clock = CPU Clock 98;// <2=> VPB Clock = CPU Clock / 2 99;// <o1.4..5> XCLKDIV: XCLK Pin 100;// <0=> XCLK Pin = CPU Clock / 4 101;// <1=> XCLK Pin = CPU Clock 102;// <2=> XCLK Pin = CPU Clock / 2 103;// </e> 104VPBDIV_SETUP EQU 0 105VPBDIV_Val EQU 0x00000000 106 107 108; Phase Locked Loop (PLL) definitions 109PLL_BASE EQU 0xE01FC080 ; PLL Base Address 110PLLCON_OFS EQU 0x00 ; PLL Control Offset 111PLLCFG_OFS EQU 0x04 ; PLL Configuration Offset 112PLLSTAT_OFS EQU 0x08 ; PLL Status Offset 113PLLFEED_OFS EQU 0x0C ; PLL Feed Offset 114PLLCON_PLLE EQU (1<<0) ; PLL Enable 115PLLCON_PLLC EQU (1<<1) ; PLL Connect 116PLLCFG_MSEL EQU (0x1F<<0) ; PLL Multiplier 117PLLCFG_PSEL EQU (0x03<<5) ; PLL Divider 118PLLSTAT_PLOCK EQU (1<<10) ; PLL Lock Status 119 120;// <e> PLL Setup 121;// <o1.0..4> MSEL: PLL Multiplier Selection 122;// <1-32><#-1> 123;// <i> M Value 124;// <o1.5..6> PSEL: PLL Divider Selection 125;// <0=> 1 <1=> 2 <2=> 4 <3=> 8 126;// <i> P Value 127;// </e> 128PLL_SETUP EQU 1 129PLLCFG_Val EQU 0x00000024 130 131 132; Memory Accelerator Module (MAM) definitions 133MAM_BASE EQU 0xE01FC000 ; MAM Base Address 134MAMCR_OFS EQU 0x00 ; MAM Control Offset 135MAMTIM_OFS EQU 0x04 ; MAM Timing Offset 136 137;// <e> MAM Setup 138;// <o1.0..1> MAM Control 139;// <0=> Disabled 140;// <1=> Partially Enabled 141;// <2=> Fully Enabled 142;// <i> Mode 143;// <o2.0..2> MAM Timing 144;// <0=> Reserved <1=> 1 <2=> 2 <3=> 3 145;// <4=> 4 <5=> 5 <6=> 6 <7=> 7 146;// <i> Fetch Cycles 147;// </e> 148MAM_SETUP EQU 1 149MAMCR_Val EQU 0x00000002 150MAMTIM_Val EQU 0x00000004 151 152 153; External Memory Controller (EMC) definitions 154EMC_BASE EQU 0xFFE00000 ; EMC Base Address 155BCFG0_OFS EQU 0x00 ; BCFG0 Offset 156BCFG1_OFS EQU 0x04 ; BCFG1 Offset 157BCFG2_OFS EQU 0x08 ; BCFG2 Offset 158BCFG3_OFS EQU 0x0C ; BCFG3 Offset 159 160;// <e> External Memory Controller (EMC) 161EMC_SETUP EQU 0 162 163;// <e> Bank Configuration 0 (BCFG0) 164;// <o1.0..3> IDCY: Idle Cycles <0-15> 165;// <o1.5..9> WST1: Wait States 1 <0-31> 166;// <o1.11..15> WST2: Wait States 2 <0-31> 167;// <o1.10> RBLE: Read Byte Lane Enable 168;// <o1.26> WP: Write Protect 169;// <o1.27> BM: Burst ROM 170;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit 171;// <2=> 32-bit <3=> Reserved 172;// </e> 173BCFG0_SETUP EQU 0 174BCFG0_Val EQU 0x0000FBEF 175 176;// <e> Bank Configuration 1 (BCFG1) 177;// <o1.0..3> IDCY: Idle Cycles <0-15> 178;// <o1.5..9> WST1: Wait States 1 <0-31> 179;// <o1.11..15> WST2: Wait States 2 <0-31> 180;// <o1.10> RBLE: Read Byte Lane Enable 181;// <o1.26> WP: Write Protect 182;// <o1.27> BM: Burst ROM 183;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit 184;// <2=> 32-bit <3=> Reserved 185;// </e> 186BCFG1_SETUP EQU 0 187BCFG1_Val EQU 0x0000FBEF 188 189;// <e> Bank Configuration 2 (BCFG2) 190;// <o1.0..3> IDCY: Idle Cycles <0-15> 191;// <o1.5..9> WST1: Wait States 1 <0-31> 192;// <o1.11..15> WST2: Wait States 2 <0-31> 193;// <o1.10> RBLE: Read Byte Lane Enable 194;// <o1.26> WP: Write Protect 195;// <o1.27> BM: Burst ROM 196;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit 197;// <2=> 32-bit <3=> Reserved 198;// </e> 199BCFG2_SETUP EQU 0 200BCFG2_Val EQU 0x0000FBEF 201 202;// <e> Bank Configuration 3 (BCFG3) 203;// <o1.0..3> IDCY: Idle Cycles <0-15> 204;// <o1.5..9> WST1: Wait States 1 <0-31> 205;// <o1.11..15> WST2: Wait States 2 <0-31> 206;// <o1.10> RBLE: Read Byte Lane Enable 207;// <o1.26> WP: Write Protect 208;// <o1.27> BM: Burst ROM 209;// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit 210;// <2=> 32-bit <3=> Reserved 211;// </e> 212BCFG3_SETUP EQU 0 213BCFG3_Val EQU 0x0000FBEF 214 215;// </e> End of EMC 216 217 218; External Memory Pins definitions 219PINSEL2 EQU 0xE002C014 ; PINSEL2 Address 220PINSEL2_Val EQU 0x0E6149E4 ; CS0..3, OE, WE, BLS0..3, 221 ; D0..31, A2..23, JTAG Pins 222 223 224 PRESERVE8 225 226 227; Area Definition and Entry Point 228; Startup Code must be linked first at Address at which it expects to run. 229 230 AREA RESET, CODE, READONLY 231 ARM 232 233 234; Exception Vectors 235; Mapped to Address 0. 236; Absolute addressing mode must be used. 237; Dummy Handlers are implemented as infinite loops which can be modified. 238 239Vectors LDR PC, Reset_Addr 240 LDR PC, Undef_Addr 241 LDR PC, SWI_Addr 242 LDR PC, PAbt_Addr 243 LDR PC, DAbt_Addr 244 NOP ; Reserved Vector 245 LDR PC, IRQ_Addr 246 LDR PC, FIQ_Addr 247 248Reset_Addr DCD Reset_Handler 249Undef_Addr DCD Undef_Handler 250SWI_Addr DCD SWI_Handler 251PAbt_Addr DCD PAbt_Handler 252DAbt_Addr DCD DAbt_Handler 253 DCD 0 ; Reserved Address 254IRQ_Addr DCD IRQ_Handler 255FIQ_Addr DCD FIQ_Handler 256 257Undef_Handler B Undef_Handler 258SWI_Handler B SWI_Handler 259PAbt_Handler B PAbt_Handler 260DAbt_Handler B DAbt_Handler 261FIQ_Handler B FIQ_Handler 262 263 264; Reset Handler 265 266 EXPORT Reset_Handler 267Reset_Handler 268 269 270; Setup External Memory Pins 271 IF :DEF:EXTERNAL_MODE 272 LDR R0, =PINSEL2 273 LDR R1, =PINSEL2_Val 274 STR R1, [R0] 275 ENDIF 276 277 278; Setup External Memory Controller 279 IF EMC_SETUP <> 0 280 LDR R0, =EMC_BASE 281 282 IF BCFG0_SETUP <> 0 283 LDR R1, =BCFG0_Val 284 STR R1, [R0, #BCFG0_OFS] 285 ENDIF 286 287 IF BCFG1_SETUP <> 0 288 LDR R1, =BCFG1_Val 289 STR R1, [R0, #BCFG1_OFS] 290 ENDIF 291 292 IF BCFG2_SETUP <> 0 293 LDR R1, =BCFG2_Val 294 STR R1, [R0, #BCFG2_OFS] 295 ENDIF 296 297 IF BCFG3_SETUP <> 0 298 LDR R1, =BCFG3_Val 299 STR R1, [R0, #BCFG3_OFS] 300 ENDIF 301 302 ENDIF ; EMC_SETUP 303 304 305; Setup VPBDIV 306 IF VPBDIV_SETUP <> 0 307 LDR R0, =VPBDIV 308 LDR R1, =VPBDIV_Val 309 STR R1, [R0] 310 ENDIF 311 312 313; Setup PLL 314 IF PLL_SETUP <> 0 315 LDR R0, =PLL_BASE 316 MOV R1, #0xAA 317 MOV R2, #0x55 318 319; Configure and Enable PLL 320 MOV R3, #PLLCFG_Val 321 STR R3, [R0, #PLLCFG_OFS] 322 MOV R3, #PLLCON_PLLE 323 STR R3, [R0, #PLLCON_OFS] 324 STR R1, [R0, #PLLFEED_OFS] 325 STR R2, [R0, #PLLFEED_OFS] 326 327; Wait until PLL Locked 328PLL_Loop LDR R3, [R0, #PLLSTAT_OFS] 329 ANDS R3, R3, #PLLSTAT_PLOCK 330 BEQ PLL_Loop 331 332; Switch to PLL Clock 333 MOV R3, #(PLLCON_PLLE:OR:PLLCON_PLLC) 334 STR R3, [R0, #PLLCON_OFS] 335 STR R1, [R0, #PLLFEED_OFS] 336 STR R2, [R0, #PLLFEED_OFS] 337 ENDIF ; PLL_SETUP 338 339 340; Setup MAM 341 IF MAM_SETUP <> 0 342 LDR R0, =MAM_BASE 343 MOV R1, #MAMTIM_Val 344 STR R1, [R0, #MAMTIM_OFS] 345 MOV R1, #MAMCR_Val 346 STR R1, [R0, #MAMCR_OFS] 347 ENDIF ; MAM_SETUP 348 349 350; Memory Mapping (when Interrupt Vectors are in RAM) 351MEMMAP EQU 0xE01FC040 ; Memory Mapping Control 352 IF :DEF:REMAP 353 LDR R0, =MEMMAP 354 IF :DEF:EXTMEM_MODE 355 MOV R1, #3 356 ELIF :DEF:RAM_MODE 357 MOV R1, #2 358 ELSE 359 MOV R1, #1 360 ENDIF 361 STR R1, [R0] 362 ENDIF 363 364 365; Initialise Interrupt System 366; ... 367 368 369; Setup Stack for each mode 370 371 LDR R0, =Stack_Top 372 373; Enter Undefined Instruction Mode and set its Stack Pointer 374 MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit 375 MOV SP, R0 376 SUB R0, R0, #UND_Stack_Size 377 378; Enter Abort Mode and set its Stack Pointer 379 MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit 380 MOV SP, R0 381 SUB R0, R0, #ABT_Stack_Size 382 383; Enter FIQ Mode and set its Stack Pointer 384 MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit 385 MOV SP, R0 386 SUB R0, R0, #FIQ_Stack_Size 387 388; Enter IRQ Mode and set its Stack Pointer 389 MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit 390 MOV SP, R0 391 SUB R0, R0, #IRQ_Stack_Size 392 393; Enter Supervisor Mode and set its Stack Pointer 394 MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit 395 MOV SP, R0 396 ; SUB R0, R0, #SVC_Stack_Size 397 398; Enter User Mode and set its Stack Pointer 399 ; RT-Thread does not use user mode 400 ; MSR CPSR_c, #Mode_USR 401 IF :DEF:__MICROLIB 402 403 EXPORT __initial_sp 404 405 ELSE 406 407 ; MOV SP, R0 408 ; SUB SL, SP, #USR_Stack_Size 409 410 ENDIF 411 412; Enter the C code 413 414 IMPORT __main 415 LDR R0, =__main 416 BX R0 417 418 IMPORT rt_interrupt_enter 419 IMPORT rt_interrupt_leave 420 IMPORT rt_thread_switch_interrupt_flag 421 IMPORT rt_interrupt_from_thread 422 IMPORT rt_interrupt_to_thread 423 IMPORT rt_hw_trap_irq 424 IMPORT rt_hw_context_switch_interrupt_do 425 426IRQ_Handler PROC 427 EXPORT IRQ_Handler 428 STMFD sp!, {r0-r12,lr} 429 BL rt_interrupt_enter 430 BL rt_hw_trap_irq 431 BL rt_interrupt_leave 432 433 ; if rt_thread_switch_interrupt_flag set, jump to 434 ; rt_hw_context_switch_interrupt_do and don't return 435 LDR r0, =rt_thread_switch_interrupt_flag 436 LDR r1, [r0] 437 CMP r1, #1 438 BEQ rt_hw_context_switch_interrupt_do 439 440 LDMFD sp!, {r0-r12,lr} 441 SUBS pc, lr, #4 442 ENDP 443 444 IF :DEF:__MICROLIB 445 446 EXPORT __heap_base 447 EXPORT __heap_limit 448 449 ELSE 450; User Initial Stack & Heap 451 AREA |.text|, CODE, READONLY 452 453 IMPORT __use_two_region_memory 454 EXPORT __user_initial_stackheap 455__user_initial_stackheap 456 457 LDR R0, = Heap_Mem 458 LDR R1, =(Stack_Mem + USR_Stack_Size) 459 LDR R2, = (Heap_Mem + Heap_Size) 460 LDR R3, = Stack_Mem 461 BX LR 462 ENDIF 463 464 END 465