1 /* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2009-12-11 Bernard first version 9 */ 10 11 #ifndef __S3C24X0_H__ 12 #define __S3C24X0_H__ 13 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 18 #include <rtthread.h> 19 20 /** 21 * @addtogroup S3C24X0 22 */ 23 /*@{*/ 24 25 // Memory control 26 #define BWSCON (*(volatile unsigned *)0x48000000) //Bus width & wait status 27 #define BANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control 28 #define BANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control 29 #define BANKCON2 (*(volatile unsigned *)0x4800000c) //BANK2 cControl 30 #define BANKCON3 (*(volatile unsigned *)0x48000010) //BANK3 control 31 #define BANKCON4 (*(volatile unsigned *)0x48000014) //BANK4 control 32 #define BANKCON5 (*(volatile unsigned *)0x48000018) //BANK5 control 33 #define BANKCON6 (*(volatile unsigned *)0x4800001c) //BANK6 control 34 #define BANKCON7 (*(volatile unsigned *)0x48000020) //BANK7 control 35 #define REFRESH (*(volatile unsigned *)0x48000024) //DRAM/SDRAM efresh 36 #define BANKSIZE (*(volatile unsigned *)0x48000028) //Flexible Bank Size 37 #define MRSRB6 (*(volatile unsigned *)0x4800002c) //Mode egister set for SDRAM 38 #define MRSRB7 (*(volatile unsigned *)0x48000030) //Mode egister set for SDRAM 39 40 41 // USB Host 42 43 44 // INTERRUPT 45 #define SRCPND (*(volatile unsigned *)0x4a000000) //Interrupt request status 46 #define INTMOD (*(volatile unsigned *)0x4a000004) //Interrupt mode control 47 #define INTMSK (*(volatile unsigned *)0x4a000008) //Interrupt mask control 48 #define PRIORITY (*(volatile unsigned *)0x4a00000c) //IRQ priority control 49 #define INTPND (*(volatile unsigned *)0x4a000010) //Interrupt request status 50 #define INTOFFSET (*(volatile unsigned *)0x4a000014) //Interruot request source offset 51 #define SUBSRCPND (*(volatile unsigned *)0x4a000018) //Sub source pending 52 #define INTSUBMSK (*(volatile unsigned *)0x4a00001c) //Interrupt sub mask 53 54 55 // DMA 56 #define DISRC0 (*(volatile unsigned *)0x4b000000) //DMA 0 Initial source 57 #define DISRCC0 (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control 58 #define DIDST0 (*(volatile unsigned *)0x4b000008) //DMA 0 Initial Destination 59 #define DIDSTC0 (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control 60 #define DCON0 (*(volatile unsigned *)0x4b000010) //DMA 0 Control 61 #define DSTAT0 (*(volatile unsigned *)0x4b000014) //DMA 0 Status 62 #define DCSRC0 (*(volatile unsigned *)0x4b000018) //DMA 0 Current source 63 #define DCDST0 (*(volatile unsigned *)0x4b00001c) //DMA 0 Current destination 64 #define DMASKTRIG0 (*(volatile unsigned *)0x4b000020) //DMA 0 Mask trigger 65 66 #define DISRC1 (*(volatile unsigned *)0x4b000040) //DMA 1 Initial source 67 #define DISRCC1 (*(volatile unsigned *)0x4b000044) //DMA 1 Initial source control 68 #define DIDST1 (*(volatile unsigned *)0x4b000048) //DMA 1 Initial Destination 69 #define DIDSTC1 (*(volatile unsigned *)0x4b00004c) //DMA 1 Initial Destination control 70 #define DCON1 (*(volatile unsigned *)0x4b000050) //DMA 1 Control 71 #define DSTAT1 (*(volatile unsigned *)0x4b000054) //DMA 1 Status 72 #define DCSRC1 (*(volatile unsigned *)0x4b000058) //DMA 1 Current source 73 #define DCDST1 (*(volatile unsigned *)0x4b00005c) //DMA 1 Current destination 74 #define DMASKTRIG1 (*(volatile unsigned *)0x4b000060) //DMA 1 Mask trigger 75 76 #define DISRC2 (*(volatile unsigned *)0x4b000080) //DMA 2 Initial source 77 #define DISRCC2 (*(volatile unsigned *)0x4b000084) //DMA 2 Initial source control 78 #define DIDST2 (*(volatile unsigned *)0x4b000088) //DMA 2 Initial Destination 79 #define DIDSTC2 (*(volatile unsigned *)0x4b00008c) //DMA 2 Initial Destination control 80 #define DCON2 (*(volatile unsigned *)0x4b000090) //DMA 2 Control 81 #define DSTAT2 (*(volatile unsigned *)0x4b000094) //DMA 2 Status 82 #define DCSRC2 (*(volatile unsigned *)0x4b000098) //DMA 2 Current source 83 #define DCDST2 (*(volatile unsigned *)0x4b00009c) //DMA 2 Current destination 84 #define DMASKTRIG2 (*(volatile unsigned *)0x4b0000a0) //DMA 2 Mask trigger 85 86 #define DISRC3 (*(volatile unsigned *)0x4b0000c0) //DMA 3 Initial source 87 #define DISRCC3 (*(volatile unsigned *)0x4b0000c4) //DMA 3 Initial source control 88 #define DIDST3 (*(volatile unsigned *)0x4b0000c8) //DMA 3 Initial Destination 89 #define DIDSTC3 (*(volatile unsigned *)0x4b0000cc) //DMA 3 Initial Destination control 90 #define DCON3 (*(volatile unsigned *)0x4b0000d0) //DMA 3 Control 91 #define DSTAT3 (*(volatile unsigned *)0x4b0000d4) //DMA 3 Status 92 #define DCSRC3 (*(volatile unsigned *)0x4b0000d8) //DMA 3 Current source 93 #define DCDST3 (*(volatile unsigned *)0x4b0000dc) //DMA 3 Current destination 94 #define DMASKTRIG3 (*(volatile unsigned *)0x4b0000e0) //DMA 3 Mask trigger 95 96 97 // CLOCK & POWER MANAGEMENT 98 #define LOCKTIME (*(volatile unsigned *)0x4c000000) //PLL lock time counter 99 #define MPLLCON (*(volatile unsigned *)0x4c000004) //MPLL Control 100 #define UPLLCON (*(volatile unsigned *)0x4c000008) //UPLL Control 101 #define CLKCON (*(volatile unsigned *)0x4c00000c) //Clock generator control 102 #define CLKSLOW (*(volatile unsigned *)0x4c000010) //Slow clock control 103 #define CLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control 104 #define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control 105 106 107 // LCD CONTROLLER 108 #define LCDCON1 (*(volatile unsigned *)0x4d000000) //LCD control 1 109 #define LCDCON2 (*(volatile unsigned *)0x4d000004) //LCD control 2 110 #define LCDCON3 (*(volatile unsigned *)0x4d000008) //LCD control 3 111 #define LCDCON4 (*(volatile unsigned *)0x4d00000c) //LCD control 4 112 #define LCDCON5 (*(volatile unsigned *)0x4d000010) //LCD control 5 113 #define LCDSADDR1 (*(volatile unsigned *)0x4d000014) //STN/TFT Frame buffer start address 1 114 #define LCDSADDR2 (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2 115 #define LCDSADDR3 (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set 116 #define REDLUT (*(volatile unsigned *)0x4d000020) //STN Red lookup table 117 #define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table 118 #define BLUELUT (*(volatile unsigned *)0x4d000028) //STN Blue lookup table 119 #define DITHMODE (*(volatile unsigned *)0x4d00004c) //STN Dithering mode 120 #define TPAL (*(volatile unsigned *)0x4d000050) //TFT Temporary palette 121 #define LCDINTPND (*(volatile unsigned *)0x4d000054) //LCD Interrupt pending 122 #define LCDSRCPND (*(volatile unsigned *)0x4d000058) //LCD Interrupt source 123 #define LCDINTMSK (*(volatile unsigned *)0x4d00005c) //LCD Interrupt mask 124 #define LPCSEL (*(volatile unsigned *)0x4d000060) //LPC3600 Control 125 #define PALETTE 0x4d000400 //Palette start address 126 127 128 // NAND flash 129 #define NFCONF (*(volatile unsigned *)0x4e000000) //NAND Flash configuration 130 #define NFCMD (*(volatile unsigned *)0x4e000004) //NADD Flash command 131 #define NFADDR (*(volatile unsigned *)0x4e000008) //NAND Flash address 132 #define NFDATA (*(volatile unsigned *)0x4e00000c) //NAND Flash data 133 #define NFSTAT (*(volatile unsigned *)0x4e000010) //NAND Flash operation status 134 #define NFECC (*(volatile unsigned *)0x4e000014) //NAND Flash ECC 135 #define NFECC0 (*(volatile unsigned *)0x4e000014) 136 #define NFECC1 (*(volatile unsigned *)0x4e000015) 137 #define NFECC2 (*(volatile unsigned *)0x4e000016) 138 139 // UART 140 #define U0BASE (*(volatile unsigned *)0x50000000) //UART 0 Line control 141 #define ULCON0 (*(volatile unsigned *)0x50000000) //UART 0 Line control 142 #define UCON0 (*(volatile unsigned *)0x50000004) //UART 0 Control 143 #define UFCON0 (*(volatile unsigned *)0x50000008) //UART 0 FIFO control 144 #define UMCON0 (*(volatile unsigned *)0x5000000c) //UART 0 Modem control 145 #define USTAT0 (*(volatile unsigned *)0x50000010) //UART 0 Tx/Rx status 146 #define URXB0 (*(volatile unsigned *)0x50000014) //UART 0 Rx error status 147 #define UFSTAT0 (*(volatile unsigned *)0x50000018) //UART 0 FIFO status 148 #define UMSTAT0 (*(volatile unsigned *)0x5000001c) //UART 0 Modem status 149 #define UBRD0 (*(volatile unsigned *)0x50000028) //UART 0 Baud ate divisor 150 151 #define U1BASE (*(volatile unsigned *)0x50004000) //UART 1 Line control 152 #define ULCON1 (*(volatile unsigned *)0x50004000) //UART 1 Line control 153 #define UCON1 (*(volatile unsigned *)0x50004004) //UART 1 Control 154 #define UFCON1 (*(volatile unsigned *)0x50004008) //UART 1 FIFO control 155 #define UMCON1 (*(volatile unsigned *)0x5000400c) //UART 1 Modem control 156 #define USTAT1 (*(volatile unsigned *)0x50004010) //UART 1 Tx/Rx status 157 #define URXB1 (*(volatile unsigned *)0x50004014) //UART 1 Rx error status 158 #define UFSTAT1 (*(volatile unsigned *)0x50004018) //UART 1 FIFO status 159 #define UMSTAT1 (*(volatile unsigned *)0x5000401c) //UART 1 Modem status 160 #define UBRD1 (*(volatile unsigned *)0x50004028) //UART 1 Baud ate divisor 161 162 #define U2BASE *(volatile unsigned *)0x50008000 //UART 2 Line control 163 #define ULCON2 (*(volatile unsigned *)0x50008000) //UART 2 Line control 164 #define UCON2 (*(volatile unsigned *)0x50008004) //UART 2 Control 165 #define UFCON2 (*(volatile unsigned *)0x50008008) //UART 2 FIFO control 166 #define UMCON2 (*(volatile unsigned *)0x5000800c) //UART 2 Modem control 167 #define USTAT2 (*(volatile unsigned *)0x50008010) //UART 2 Tx/Rx status 168 #define URXB2 (*(volatile unsigned *)0x50008014) //UART 2 Rx error status 169 #define UFSTAT2 (*(volatile unsigned *)0x50008018) //UART 2 FIFO status 170 #define UMSTAT2 (*(volatile unsigned *)0x5000801c) //UART 2 Modem status 171 #define UBRD2 (*(volatile unsigned *)0x50008028) //UART 2 Baud ate divisor 172 173 #ifdef __BIG_ENDIAN 174 #define UTXH0 (*(volatile unsigned char *)0x50000023) //UART 0 Transmission Hold 175 #define URXH0 (*(volatile unsigned char *)0x50000027) //UART 0 Receive buffer 176 #define UTXH1 (*(volatile unsigned char *)0x50004023) //UART 1 Transmission Hold 177 #define URXH1 (*(volatile unsigned char *)0x50004027) //UART 1 Receive buffer 178 #define UTXH2 (*(volatile unsigned char *)0x50008023) //UART 2 Transmission Hold 179 #define URXH2 (*(volatile unsigned char *)0x50008027) //UART 2 Receive buffer 180 181 #define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch) 182 #define RdURXH0() (*(volatile unsigned char *)0x50000027) 183 #define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch) 184 #define RdURXH1() (*(volatile unsigned char *)0x50004027) 185 #define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch) 186 #define RdURXH2() (*(volatile unsigned char *)0x50008027) 187 188 #else //Little Endian 189 #define UTXH0 (*(volatile unsigned char *)0x50000020) //UART 0 Transmission Hold 190 #define URXH0 (*(volatile unsigned char *)0x50000024) //UART 0 Receive buffer 191 #define UTXH1 (*(volatile unsigned char *)0x50004020) //UART 1 Transmission Hold 192 #define URXH1 (*(volatile unsigned char *)0x50004024) //UART 1 Receive buffer 193 #define UTXH2 (*(volatile unsigned char *)0x50008020) //UART 2 Transmission Hold 194 #define URXH2 (*(volatile unsigned char *)0x50008024) //UART 2 Receive buffer 195 196 #define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch) 197 #define RdURXH0() (*(volatile unsigned char *)0x50000024) 198 #define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch) 199 #define RdURXH1() (*(volatile unsigned char *)0x50004024) 200 #define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch) 201 #define RdURXH2() (*(volatile unsigned char *)0x50008024) 202 203 #endif 204 205 206 // PWM TIMER 207 #define TCFG0 (*(volatile unsigned *)0x51000000) //Timer 0 configuration 208 #define TCFG1 (*(volatile unsigned *)0x51000004) //Timer 1 configuration 209 #define TCON (*(volatile unsigned *)0x51000008) //Timer control 210 #define TCNTB0 (*(volatile unsigned *)0x5100000c) //Timer count buffer 0 211 #define TCMPB0 (*(volatile unsigned *)0x51000010) //Timer compare buffer 0 212 #define TCNTO0 (*(volatile unsigned *)0x51000014) //Timer count observation 0 213 #define TCNTB1 (*(volatile unsigned *)0x51000018) //Timer count buffer 1 214 #define TCMPB1 (*(volatile unsigned *)0x5100001c) //Timer compare buffer 1 215 #define TCNTO1 (*(volatile unsigned *)0x51000020) //Timer count observation 1 216 #define TCNTB2 (*(volatile unsigned *)0x51000024) //Timer count buffer 2 217 #define TCMPB2 (*(volatile unsigned *)0x51000028) //Timer compare buffer 2 218 #define TCNTO2 (*(volatile unsigned *)0x5100002c) //Timer count observation 2 219 #define TCNTB3 (*(volatile unsigned *)0x51000030) //Timer count buffer 3 220 #define TCMPB3 (*(volatile unsigned *)0x51000034) //Timer compare buffer 3 221 #define TCNTO3 (*(volatile unsigned *)0x51000038) //Timer count observation 3 222 #define TCNTB4 (*(volatile unsigned *)0x5100003c) //Timer count buffer 4 223 #define TCNTO4 (*(volatile unsigned *)0x51000040) //Timer count observation 4 224 225 // Added for 2440 226 #define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only) 227 #define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0 228 #define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1 229 #define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register 230 231 232 // USB DEVICE 233 #ifdef __BIG_ENDIAN 234 #define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) //Function address 235 #define PWR_REG (*(volatile unsigned char *)0x52000147) //Power management 236 #define EP_INT_REG (*(volatile unsigned char *)0x5200014b) //EP Interrupt pending and clear 237 #define USB_INT_REG (*(volatile unsigned char *)0x5200015b) //USB Interrupt pending and clear 238 #define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015f) //Interrupt enable 239 #define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016f) 240 #define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) //Frame number lower byte 241 #define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) //Frame number higher byte 242 #define INDEX_REG (*(volatile unsigned char *)0x5200017b) //Register index 243 #define MAXP_REG (*(volatile unsigned char *)0x52000183) //Endpoint max packet 244 #define EP0_CSR (*(volatile unsigned char *)0x52000187) //Endpoint 0 status 245 #define IN_CSR1_REG (*(volatile unsigned char *)0x52000187) //In endpoint control status 246 #define IN_CSR2_REG (*(volatile unsigned char *)0x5200018b) 247 #define OUT_CSR1_REG (*(volatile unsigned char *)0x52000193) //Out endpoint control status 248 #define OUT_CSR2_REG (*(volatile unsigned char *)0x52000197) 249 #define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019b) //Endpoint out write count 250 #define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019f) 251 #define EP0_FIFO (*(volatile unsigned char *)0x520001c3) //Endpoint 0 FIFO 252 #define EP1_FIFO (*(volatile unsigned char *)0x520001c7) //Endpoint 1 FIFO 253 #define EP2_FIFO (*(volatile unsigned char *)0x520001cb) //Endpoint 2 FIFO 254 #define EP3_FIFO (*(volatile unsigned char *)0x520001cf) //Endpoint 3 FIFO 255 #define EP4_FIFO (*(volatile unsigned char *)0x520001d3) //Endpoint 4 FIFO 256 #define EP1_DMA_CON (*(volatile unsigned char *)0x52000203) //EP1 DMA interface control 257 #define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) //EP1 DMA Tx unit counter 258 #define EP1_DMA_FIFO (*(volatile unsigned char *)0x5200020b) //EP1 DMA Tx FIFO counter 259 #define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020f) //EP1 DMA total Tx counter 260 #define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000213) 261 #define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000217) 262 #define EP2_DMA_CON (*(volatile unsigned char *)0x5200021b) //EP2 DMA interface control 263 #define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021f) //EP2 DMA Tx unit counter 264 #define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) //EP2 DMA Tx FIFO counter 265 #define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000227) //EP2 DMA total Tx counter 266 #define EP2_DMA_TTC_M (*(volatile unsigned char *)0x5200022b) 267 #define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022f) 268 #define EP3_DMA_CON (*(volatile unsigned char *)0x52000243) //EP3 DMA interface control 269 #define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) //EP3 DMA Tx unit counter 270 #define EP3_DMA_FIFO (*(volatile unsigned char *)0x5200024b) //EP3 DMA Tx FIFO counter 271 #define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024f) //EP3 DMA total Tx counter 272 #define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000253) 273 #define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000257) 274 #define EP4_DMA_CON (*(volatile unsigned char *)0x5200025b) //EP4 DMA interface control 275 #define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025f) //EP4 DMA Tx unit counter 276 #define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) //EP4 DMA Tx FIFO counter 277 #define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000267) //EP4 DMA total Tx counter 278 #define EP4_DMA_TTC_M (*(volatile unsigned char *)0x5200026b) 279 #define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026f) 280 281 #else // Little Endian 282 #define FUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) //Function address 283 #define PWR_REG (*(volatile unsigned char *)0x52000144) //Power management 284 #define EP_INT_REG (*(volatile unsigned char *)0x52000148) //EP Interrupt pending and clear 285 #define USB_INT_REG (*(volatile unsigned char *)0x52000158) //USB Interrupt pending and clear 286 #define EP_INT_EN_REG (*(volatile unsigned char *)0x5200015c) //Interrupt enable 287 #define USB_INT_EN_REG (*(volatile unsigned char *)0x5200016c) 288 #define FRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) //Frame number lower byte 289 #define FRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) //Frame number higher byte 290 #define INDEX_REG (*(volatile unsigned char *)0x52000178) //Register index 291 #define MAXP_REG (*(volatile unsigned char *)0x52000180) //Endpoint max packet 292 #define EP0_CSR (*(volatile unsigned char *)0x52000184) //Endpoint 0 status 293 #define IN_CSR1_REG (*(volatile unsigned char *)0x52000184) //In endpoint control status 294 #define IN_CSR2_REG (*(volatile unsigned char *)0x52000188) 295 #define OUT_CSR1_REG (*(volatile unsigned char *)0x52000190) //Out endpoint control status 296 #define OUT_CSR2_REG (*(volatile unsigned char *)0x52000194) 297 #define OUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) //Endpoint out write count 298 #define OUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019c) 299 #define EP0_FIFO (*(volatile unsigned char *)0x520001c0) //Endpoint 0 FIFO 300 #define EP1_FIFO (*(volatile unsigned char *)0x520001c4) //Endpoint 1 FIFO 301 #define EP2_FIFO (*(volatile unsigned char *)0x520001c8) //Endpoint 2 FIFO 302 #define EP3_FIFO (*(volatile unsigned char *)0x520001cc) //Endpoint 3 FIFO 303 #define EP4_FIFO (*(volatile unsigned char *)0x520001d0) //Endpoint 4 FIFO 304 #define EP1_DMA_CON (*(volatile unsigned char *)0x52000200) //EP1 DMA interface control 305 #define EP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) //EP1 DMA Tx unit counter 306 #define EP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) //EP1 DMA Tx FIFO counter 307 #define EP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020c) //EP1 DMA total Tx counter 308 #define EP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210) 309 #define EP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214) 310 #define EP2_DMA_CON (*(volatile unsigned char *)0x52000218) //EP2 DMA interface control 311 #define EP2_DMA_UNIT (*(volatile unsigned char *)0x5200021c) //EP2 DMA Tx unit counter 312 #define EP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) //EP2 DMA Tx FIFO counter 313 #define EP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) //EP2 DMA total Tx counter 314 #define EP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228) 315 #define EP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022c) 316 #define EP3_DMA_CON (*(volatile unsigned char *)0x52000240) //EP3 DMA interface control 317 #define EP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) //EP3 DMA Tx unit counter 318 #define EP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) //EP3 DMA Tx FIFO counter 319 #define EP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024c) //EP3 DMA total Tx counter 320 #define EP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250) 321 #define EP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254) 322 #define EP4_DMA_CON (*(volatile unsigned char *)0x52000258) //EP4 DMA interface control 323 #define EP4_DMA_UNIT (*(volatile unsigned char *)0x5200025c) //EP4 DMA Tx unit counter 324 #define EP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) //EP4 DMA Tx FIFO counter 325 #define EP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) //EP4 DMA total Tx counter 326 #define EP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268) 327 #define EP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026c) 328 #endif // __BIG_ENDIAN 329 330 331 // WATCH DOG TIMER 332 #define WTCON (*(volatile unsigned *)0x53000000) //Watch-dog timer mode 333 #define WTDAT (*(volatile unsigned *)0x53000004) //Watch-dog timer data 334 #define WTCNT (*(volatile unsigned *)0x53000008) //Eatch-dog timer count 335 336 337 // IIC 338 #define IICCON (*(volatile unsigned *)0x54000000) //IIC control 339 #define IICSTAT (*(volatile unsigned *)0x54000004) //IIC status 340 #define IICADD (*(volatile unsigned *)0x54000008) //IIC address 341 #define IICDS (*(volatile unsigned *)0x5400000c) //IIC data shift 342 343 344 // IIS 345 #define IISCON (*(volatile unsigned *)0x55000000) //IIS Control 346 #define IISMOD (*(volatile unsigned *)0x55000004) //IIS Mode 347 #define IISPSR (*(volatile unsigned *)0x55000008) //IIS Prescaler 348 #define IISFCON (*(volatile unsigned *)0x5500000c) //IIS FIFO control 349 350 #ifdef __BIG_ENDIAN 351 #define IISFIFO ((volatile unsigned short *)0x55000012) //IIS FIFO entry 352 353 #else //Little Endian 354 #define IISFIFO ((volatile unsigned short *)0x55000010) //IIS FIFO entry 355 356 #endif 357 358 359 // I/O PORT 360 #define GPACON (*(volatile unsigned *)0x56000000) //Port A control 361 #define GPADAT (*(volatile unsigned *)0x56000004) //Port A data 362 363 #define GPBCON (*(volatile unsigned *)0x56000010) //Port B control 364 #define GPBDAT (*(volatile unsigned *)0x56000014) //Port B data 365 #define GPBUP (*(volatile unsigned *)0x56000018) //Pull-up control B 366 367 #define GPCCON (*(volatile unsigned *)0x56000020) //Port C control 368 #define GPCDAT (*(volatile unsigned *)0x56000024) //Port C data 369 #define GPCUP (*(volatile unsigned *)0x56000028) //Pull-up control C 370 371 #define GPDCON (*(volatile unsigned *)0x56000030) //Port D control 372 #define GPDDAT (*(volatile unsigned *)0x56000034) //Port D data 373 #define GPDUP (*(volatile unsigned *)0x56000038) //Pull-up control D 374 375 #define GPECON (*(volatile unsigned *)0x56000040) //Port E control 376 #define GPEDAT (*(volatile unsigned *)0x56000044) //Port E data 377 #define GPEUP (*(volatile unsigned *)0x56000048) //Pull-up control E 378 379 #define GPFCON (*(volatile unsigned *)0x56000050) //Port F control 380 #define GPFDAT (*(volatile unsigned *)0x56000054) //Port F data 381 #define GPFUP (*(volatile unsigned *)0x56000058) //Pull-up control F 382 383 #define GPGCON (*(volatile unsigned *)0x56000060) //Port G control 384 #define GPGDAT (*(volatile unsigned *)0x56000064) //Port G data 385 #define GPGUP (*(volatile unsigned *)0x56000068) //Pull-up control G 386 387 #define GPHCON (*(volatile unsigned *)0x56000070) //Port H control 388 #define GPHDAT (*(volatile unsigned *)0x56000074) //Port H data 389 #define GPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H 390 391 #define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control 392 #define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data 393 #define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J 394 395 #define MISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control 396 #define DCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control 397 #define EXTINT0 (*(volatile unsigned *)0x56000088) //External interrupt control egister 0 398 #define EXTINT1 (*(volatile unsigned *)0x5600008c) //External interrupt control egister 1 399 #define EXTINT2 (*(volatile unsigned *)0x56000090) //External interrupt control egister 2 400 #define EINTFLT0 (*(volatile unsigned *)0x56000094) //Reserved 401 #define EINTFLT1 (*(volatile unsigned *)0x56000098) //Reserved 402 #define EINTFLT2 (*(volatile unsigned *)0x5600009c) //External interrupt filter control egister 2 403 #define EINTFLT3 (*(volatile unsigned *)0x560000a0) //External interrupt filter control egister 3 404 #define EINTMASK (*(volatile unsigned *)0x560000a4) //External interrupt mask 405 #define EINTPEND (*(volatile unsigned *)0x560000a8) //External interrupt pending 406 #define GSTATUS0 (*(volatile unsigned *)0x560000ac) //External pin status 407 #define GSTATUS1 (*(volatile unsigned *)0x560000b0) //Chip ID(0x32410000) 408 #define GSTATUS2 (*(volatile unsigned *)0x560000b4) //Reset type 409 #define GSTATUS3 (*(volatile unsigned *)0x560000b8) //Saved data0(32-bit) before entering POWER_OFF mode 410 #define GSTATUS4 (*(volatile unsigned *)0x560000bc) //Saved data0(32-bit) before entering POWER_OFF mode 411 412 413 // RTC 414 #ifdef __BIG_ENDIAN 415 #define RTCCON (*(volatile unsigned char *)0x57000043) //RTC control 416 #define TICNT (*(volatile unsigned char *)0x57000047) //Tick time count 417 #define RTCALM (*(volatile unsigned char *)0x57000053) //RTC alarm control 418 #define ALMSEC (*(volatile unsigned char *)0x57000057) //Alarm second 419 #define ALMMIN (*(volatile unsigned char *)0x5700005b) //Alarm minute 420 #define ALMHOUR (*(volatile unsigned char *)0x5700005f) //Alarm Hour 421 #define ALMDATE (*(volatile unsigned char *)0x57000063) //Alarm day <-- May 06, 2002 SOP 422 #define ALMMON (*(volatile unsigned char *)0x57000067) //Alarm month 423 #define ALMYEAR (*(volatile unsigned char *)0x5700006b) //Alarm year 424 #define RTCRST (*(volatile unsigned char *)0x5700006f) //RTC ound eset 425 #define BCDSEC (*(volatile unsigned char *)0x57000073) //BCD second 426 #define BCDMIN (*(volatile unsigned char *)0x57000077) //BCD minute 427 #define BCDHOUR (*(volatile unsigned char *)0x5700007b) //BCD hour 428 #define BCDDATE (*(volatile unsigned char *)0x5700007f) //BCD day <-- May 06, 2002 SOP 429 #define BCDDAY (*(volatile unsigned char *)0x57000083) //BCD date <-- May 06, 2002 SOP 430 #define BCDMON (*(volatile unsigned char *)0x57000087) //BCD month 431 #define BCDYEAR (*(volatile unsigned char *)0x5700008b) //BCD year 432 433 #else //Little Endian 434 #define RTCCON (*(volatile unsigned char *)0x57000040) //RTC control 435 #define TICNT (*(volatile unsigned char *)0x57000044) //Tick time count 436 #define RTCALM (*(volatile unsigned char *)0x57000050) //RTC alarm control 437 #define ALMSEC (*(volatile unsigned char *)0x57000054) //Alarm second 438 #define ALMMIN (*(volatile unsigned char *)0x57000058) //Alarm minute 439 #define ALMHOUR (*(volatile unsigned char *)0x5700005c) //Alarm Hour 440 #define ALMDATE (*(volatile unsigned char *)0x57000060) //Alarm day <-- May 06, 2002 SOP 441 #define ALMMON (*(volatile unsigned char *)0x57000064) //Alarm month 442 #define ALMYEAR (*(volatile unsigned char *)0x57000068) //Alarm year 443 #define RTCRST (*(volatile unsigned char *)0x5700006c) //RTC ound eset 444 #define BCDSEC (*(volatile unsigned char *)0x57000070) //BCD second 445 #define BCDMIN (*(volatile unsigned char *)0x57000074) //BCD minute 446 #define BCDHOUR (*(volatile unsigned char *)0x57000078) //BCD hour 447 #define BCDDATE (*(volatile unsigned char *)0x5700007c) //BCD day <-- May 06, 2002 SOP 448 #define BCDDAY (*(volatile unsigned char *)0x57000080) //BCD date <-- May 06, 2002 SOP 449 #define BCDMON (*(volatile unsigned char *)0x57000084) //BCD month 450 #define BCDYEAR (*(volatile unsigned char *)0x57000088) //BCD year 451 #endif //RTC 452 453 454 // ADC 455 #define ADCCON (*(volatile unsigned *)0x58000000) //ADC control 456 #define ADCTSC (*(volatile unsigned *)0x58000004) //ADC touch screen control 457 #define ADCDLY (*(volatile unsigned *)0x58000008) //ADC start or Interval Delay 458 #define ADCDAT0 (*(volatile unsigned *)0x5800000c) //ADC conversion data 0 459 #define ADCDAT1 (*(volatile unsigned *)0x58000010) //ADC conversion data 1 460 461 // SPI 462 #define SPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control 463 #define SPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status 464 #define SPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control 465 #define SPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud ate prescaler 466 #define SPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data 467 #define SPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data 468 469 #define SPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control 470 #define SPSTA1 (*(volatile unsigned *)0x59000024) //SPI1 status 471 #define SPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control 472 #define SPPRE1 (*(volatile unsigned *)0x5900002c) //SPI1 baud ate prescaler 473 #define SPTDAT1 (*(volatile unsigned *)0x59000030) //SPI1 Tx data 474 #define SPRDAT1 (*(volatile unsigned *)0x59000034) //SPI1 Rx data 475 476 477 // SD Interface 478 #define SDICON (*(volatile unsigned *)0x5a000000) //SDI control 479 #define SDIPRE (*(volatile unsigned *)0x5a000004) //SDI baud ate prescaler 480 #define SDICARG (*(volatile unsigned *)0x5a000008) //SDI command argument 481 #define SDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control 482 #define SDICSTA (*(volatile unsigned *)0x5a000010) //SDI command status 483 #define SDIRSP0 (*(volatile unsigned *)0x5a000014) //SDI esponse 0 484 #define SDIRSP1 (*(volatile unsigned *)0x5a000018) //SDI esponse 1 485 #define SDIRSP2 (*(volatile unsigned *)0x5a00001c) //SDI esponse 2 486 #define SDIRSP3 (*(volatile unsigned *)0x5a000020) //SDI esponse 3 487 #define SDIDTIMER (*(volatile unsigned *)0x5a000024) //SDI data/busy timer 488 #define SDIBSIZE (*(volatile unsigned *)0x5a000028) //SDI block size 489 #define SDIDCON (*(volatile unsigned *)0x5a00002c) //SDI data control 490 #define SDIDCNT (*(volatile unsigned *)0x5a000030) //SDI data emain counter 491 #define SDIDSTA (*(volatile unsigned *)0x5a000034) //SDI data status 492 #define SDIFSTA (*(volatile unsigned *)0x5a000038) //SDI FIFO status 493 #define SDIIMSK (*(volatile unsigned *)0x5a000040) //SDI interrupt mask 494 495 #ifdef __BIG_ENDIAN /* edited for 2440A */ 496 #define SDIDAT (*(volatile unsigned *)0x5a00004c) 497 #else // Little Endian 498 #define SDIDAT (*(volatile unsigned *)0x5a000040) 499 #endif //SD Interface 500 501 // PENDING BIT 502 #define INTEINT0 (0) 503 #define INTEINT1 (1) 504 #define INTEINT2 (2) 505 #define INTEINT3 (3) 506 #define INTEINT4_7 (4) 507 #define INTEINT8_23 (5) 508 #define INTNOTUSED6 (6) 509 #define INTBAT_FLT (7) 510 #define INTTICK (8) 511 #define INTWDT (9) 512 #define INTTIMER0 (10) 513 #define INTTIMER1 (11) 514 #define INTTIMER2 (12) 515 #define INTTIMER3 (13) 516 #define INTTIMER4 (14) 517 #define INTUART2 (15) 518 #define INTLCD (16) 519 #define INTDMA0 (17) 520 #define INTDMA1 (18) 521 #define INTDMA2 (19) 522 #define INTDMA3 (20) 523 #define INTSDI (21) 524 #define INTSPI0 (22) 525 #define INTUART1 (23) 526 //#define INTNOTUSED24 (24) 527 #define INTNIC (24) 528 #define INTUSBD (25) 529 #define INTUSBH (26) 530 #define INTIIC (27) 531 #define INTUART0 (28) 532 #define INTSPI1 (29) 533 #define INTRTC (30) 534 #define INTADC (31) 535 #define BIT_ALLMSK (0xffffffff) 536 537 #define BIT_SUB_ALLMSK (0x7ff) 538 #define INTSUB_ADC (10) 539 #define INTSUB_TC (9) 540 #define INTSUB_ERR2 (8) 541 #define INTSUB_TXD2 (7) 542 #define INTSUB_RXD2 (6) 543 #define INTSUB_ERR1 (5) 544 #define INTSUB_TXD1 (4) 545 #define INTSUB_RXD1 (3) 546 #define INTSUB_ERR0 (2) 547 #define INTSUB_TXD0 (1) 548 #define INTSUB_RXD0 (0) 549 550 #define BIT_SUB_ADC (0x1<<10) 551 #define BIT_SUB_TC (0x1<<9) 552 #define BIT_SUB_ERR2 (0x1<<8) 553 #define BIT_SUB_TXD2 (0x1<<7) 554 #define BIT_SUB_RXD2 (0x1<<6) 555 #define BIT_SUB_ERR1 (0x1<<5) 556 #define BIT_SUB_TXD1 (0x1<<4) 557 #define BIT_SUB_RXD1 (0x1<<3) 558 #define BIT_SUB_ERR0 (0x1<<2) 559 #define BIT_SUB_TXD0 (0x1<<1) 560 #define BIT_SUB_RXD0 (0x1<<0) 561 562 #define ClearPending(bit) {SRCPND = bit;INTPND = bit;INTPND;} 563 //Wait until INTPND is changed for the case that the ISR is very short. 564 565 #define INTGLOBAL 32 566 567 /*****************************/ 568 /* CPU Mode */ 569 /*****************************/ 570 #define USERMODE 0x10 571 #define FIQMODE 0x11 572 #define IRQMODE 0x12 573 #define SVCMODE 0x13 574 #define ABORTMODE 0x17 575 #define UNDEFMODE 0x1b 576 #define MODEMASK 0x1f 577 #define NOINT 0xc0 578 579 struct rt_hw_register 580 { 581 rt_uint32_t r0; 582 rt_uint32_t r1; 583 rt_uint32_t r2; 584 rt_uint32_t r3; 585 rt_uint32_t r4; 586 rt_uint32_t r5; 587 rt_uint32_t r6; 588 rt_uint32_t r7; 589 rt_uint32_t r8; 590 rt_uint32_t r9; 591 rt_uint32_t r10; 592 rt_uint32_t fp; 593 rt_uint32_t ip; 594 rt_uint32_t sp; 595 rt_uint32_t lr; 596 rt_uint32_t pc; 597 rt_uint32_t cpsr; 598 rt_uint32_t ORIG_r0; 599 }; 600 601 #ifdef __cplusplus 602 } 603 #endif 604 605 /*@}*/ 606 607 #endif 608