1 /** 2 ****************************************************************************** 3 * @file x1000_aic.h 4 * @author Urey 5 * @version V1.0.0 6 * @date 2017��2��20�� 7 * @brief TODO 8 ****************************************************************************** 9 **/ 10 11 12 #ifndef _X1000_AIC_H_ 13 #define _X1000_AIC_H_ 14 15 #ifdef __cplusplus 16 extern "C" { 17 #endif 18 19 #define AIC_FR (AIC_BASE + 0x00) 20 #define AIC_CR (AIC_BASE + 0x04) 21 #define AIC_ACCR1 (AIC_BASE + 0x08) 22 #define AIC_ACCR2 (AIC_BASE + 0x0c) 23 #define AIC_I2SCR (AIC_BASE + 0x10) 24 #define AIC_SR (AIC_BASE + 0x14) 25 #define AIC_ACSR (AIC_BASE + 0x18) 26 #define AIC_I2SSR (AIC_BASE + 0x1c) 27 #define AIC_ACCAR (AIC_BASE + 0x20) 28 #define AIC_ACCDR (AIC_BASE + 0x24) 29 #define AIC_ACSAR (AIC_BASE + 0x28) 30 #define AIC_ACSDR (AIC_BASE + 0x2c) 31 #define AIC_I2SDIV (AIC_BASE + 0x30) 32 #define AIC_DR (AIC_BASE + 0x34) 33 34 #define SPDIF_ENA (AIC_BASE + 0x80) 35 #define SPDIF_CTRL (AIC_BASE + 0x84) 36 #define SPDIF_STATE (AIC_BASE + 0x88) 37 #define SPDIF_CFG1 (AIC_BASE + 0x8c) 38 #define SPDIF_CFG2 (AIC_BASE + 0x90) 39 #define SPDIF_FIFO (AIC_BASE + 0x94) 40 41 #define ICDC_CKCFG (AIC_BASE + 0xa0) 42 #define ICDC_RGADW (AIC_BASE + 0xa4) 43 #define ICDC_RGDATA (AIC_BASE + 0xa8) 44 45 46 /* AIC_FR definition */ 47 #define AIC_FR_RFTH_LSB 24 48 #define AIC_FR_RFTH(x) ( ( (x)/2 - 1 ) << AIC_FR_RFTH_LSB) // 2, 4, ..., 32 49 #define AIC_FR_RFTH_MASK BITS_H2L(27, AIC_FR_RFTH_LSB) 50 51 #define AIC_FR_TFTH_LSB 16 52 #define AIC_FR_TFTH(x) ( ( (x)/2 ) << AIC_FR_TFTH_LSB) // 2, 4, ..., 32 53 #define AIC_FR_TFTH_MASK BITS_H2L(20, AIC_FR_TFTH_LSB) 54 55 /* new@4770 */ 56 #define AIC_FR_IBCKD BIT10 57 58 /* new@4770 */ 59 #define AIC_FR_ISYNCD BIT9 60 61 /* new@4770 */ 62 #define IC_FR_DMODE BIT8 63 64 #define AIC_FR_LSMP BIT6 65 #define AIC_FR_ICDC BIT5 66 #define AIC_FR_AUSEL BIT4 67 #define AIC_FR_RST BIT3 68 #define AIC_FR_BCKD BIT2 69 #define AIC_FR_SYNCD BIT1 70 #define AIC_FR_ENB BIT0 71 72 73 /* AIC_CR definition */ 74 #define AIC_CR_PACK16 BIT28 75 76 #define AIC_CR_CHANNEL_LSB 24 77 #define AIC_CR_CHANNEL_MASK BITS_H2L(26, 24) 78 #define AIC_CR_CHANNEL_MONO (0x0 << AIC_CR_CHANNEL_LSB) 79 #define AIC_CR_CHANNEL_STEREO (0x1 << AIC_CR_CHANNEL_LSB) 80 #define AIC_CR_CHANNEL_4CHNL (0x3 << AIC_CR_CHANNEL_LSB) 81 #define AIC_CR_CHANNEL_6CHNL (0x5 << AIC_CR_CHANNEL_LSB) 82 #define AIC_CR_CHANNEL_8CHNL (0x7 << AIC_CR_CHANNEL_LSB) 83 84 #define AIC_CR_OSS_LSB 19 85 #define AIC_CR_OSS_MASK BITS_H2L(21, AIC_CR_OSS_LSB) 86 #define AIC_CR_OSS(n) (((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_OSS_LSB) /* n = 8, 16, 18, 20, 24 */ 87 88 #define AIC_CR_ISS_LSB 16 89 #define AIC_CR_ISS_MASK BITS_H2L(18, AIC_CR_ISS_LSB) 90 #define AIC_CR_ISS(n) (((n) > 18 ? (n)/6 : (n)/9) << AIC_CR_ISS_LSB) /* n = 8, 16, 18, 20, 24 */ 91 92 #define AIC_CR_RDMS BIT15 93 #define AIC_CR_TDMS BIT14 94 #define AIC_CR_M2S BIT11 95 #define AIC_CR_ENDSW BIT10 96 #define AIC_CR_AVSTSU BIT9 97 #define AIC_CR_TFLUSH BIT8 98 #define AIC_CR_RFLUSH BIT7 99 #define AIC_CR_EROR BIT6 100 #define AIC_CR_ETUR BIT5 101 #define AIC_CR_ERFS BIT4 102 #define AIC_CR_ETFS BIT3 103 #define AIC_CR_ENLBF BIT2 104 #define AIC_CR_ERPL BIT1 105 #define AIC_CR_EREC BIT0 106 107 /* AIC controller AC-link control register 1(ACCR1) */ 108 #define AIC_ACCR1_RS_LSB 16 109 #define AIC_ACCR1_RS_MASK BITS_H2L(25, AIC_ACCR1_RS_LSB) 110 #define AIC_ACCR1_RS_SLOT(n) ((1 << ((n) - 3)) << AIC_ACCR1_RS_LSB) /* n = 3 .. 12 */ 111 112 #define AIC_ACCR1_XS_LSB 0 113 #define AIC_ACCR1_XS_MASK BITS_H2L(9, AIC_ACCR1_XS_LSB) 114 #define AIC_ACCR1_XS_SLOT(n) ((1 << ((n) - 3)) << AIC_ACCR1_XS_LSB) /* n = 3 .. 12 */ 115 116 /* AIC controller AC-link control register 2 (ACCR2) */ 117 #define AIC_ACCR2_ERSTO BIT18 118 #define AIC_ACCR2_ESADR BIT17 119 #define AIC_ACCR2_ECADT BIT16 120 #define AIC_ACCR2_SO BIT3 121 #define AIC_ACCR2_SR BIT2 122 #define AIC_ACCR2_SS BIT1 123 #define AIC_ACCR2_SA BIT0 124 125 /* AIC controller i2s/msb-justified control register (I2SCR) */ 126 #define AIC_I2SCR_RFIRST BIT17 127 #define AIC_I2SCR_SWLH BIT16 128 #define AIC_I2SCR_ISTPBK BIT13 129 #define AIC_I2SCR_STPBK BIT12 130 #define AIC_I2SCR_ESCLK BIT4 131 #define AIC_I2SCR_AMSL BIT0 132 133 /* AIC controller FIFO status register (AICSR) */ 134 #define AIC_SR_RFL_LSB 24 135 #define AIC_SR_RFL_MASK BITS_H2L(29, AIC_SR_RFL_LSB) 136 137 #define AIC_SR_TFL_LSB 8 138 #define AIC_SR_TFL_MASK BITS_H2L(13, AIC_SR_TFL_LSB) 139 140 #define AIC_SR_ROR BIT6 141 #define AIC_SR_TUR BIT5 142 #define AIC_SR_RFS BIT4 143 #define AIC_SR_TFS BIT3 144 145 /* AIC controller AC-link status register (ACSR) */ 146 #define AIC_ACSR_SLTERR BIT21 147 #define AIC_ACSR_CRDY BIT20 148 #define AIC_ACSR_CLPM BIT19 149 #define AIC_ACSR_RSTO BIT18 150 #define AIC_ACSR_SADR BIT17 151 #define AIC_ACSR_CADT BIT16 152 153 /* AIC controller I2S/MSB-justified status register (I2SSR) */ 154 #define AIC_I2SSR_CHBSY BIT5 155 #define AIC_I2SSR_TBSY BIT4 156 #define AIC_I2SSR_RBSY BIT3 157 #define AIC_I2SSR_BSY BIT2 158 159 /* AIC controller AC97 codec command address register (ACCAR) */ 160 #define AIC_ACCAR_CAR_LSB 0 161 #define AIC_ACCAR_CAR_MASK BITS_H2L(19, AIC_ACCAR_CAR_LSB) 162 163 164 /* AIC controller AC97 codec command data register (ACCDR) */ 165 #define AIC_ACCDR_CDR_LSB 0 166 #define AIC_ACCDR_CDR_MASK BITS_H2L(19, AIC_ACCDR_CDR_LSB) 167 168 /* AC97 read and write macro based on ACCAR and ACCDR */ 169 #define AC97_READ_CMD BIT19 170 #define AC97_WRITE_CMD (BIT19 & ~BIT19) 171 172 #define AC97_INDEX_LSB 12 173 #define AC97_INDEX_MASK BITS_H2L(18, AC97_INDEX_LSB) 174 175 #define AC97_DATA_LSB 4 176 #define AC97_DATA_MASK BITS_H2L(19, AC97_DATA_LSB) 177 178 /* AIC controller AC97 codec status address register (ACSAR) */ 179 #define AIC_ACSAR_SAR_LSB 0 180 #define AIC_ACSAR_SAR_MASK BITS_H2L(19, AIC_ACSAR_SAR_LSB) 181 182 /* AIC controller AC97 codec status data register (ACSDR) */ 183 #define AIC_ACSDR_SDR_LSB 0 184 #define AIC_ACSDR_SDR_MASK BITS_H2L(19, AIC_ACSDR_SDR_LSB) 185 186 /* AIC controller I2S/MSB-justified clock divider register (I2SDIV) */ 187 #define AIC_I2SDIV_IDIV_LSB 16 188 #define AIC_I2SDIV_IDIV_MASK BITS_H2L(24, AIC_I2SDIV_IDIV_LSB) 189 #define AIC_I2SDIV_DIV_LSB 0 190 #define AIC_I2SDIV_DIV_MASK BITS_H2L(8, AIC_I2SDIV_DIV_LSB) 191 192 /* SPDIF enable register (SPDIF_ENA) */ 193 #define SPDIF_ENA_SPEN BIT0 194 195 /* SPDIF control register (SPDIF_CTRL) */ 196 #define SPDIF_CTRL_DMAEN BIT15 197 #define SPDIF_CTRL_DTYPE BIT14 198 #define SPDIF_CTRL_SIGN BIT13 199 #define SPDIF_CTRL_INVALID BIT12 200 #define SPDIF_CTRL_RST BIT11 201 #define SPDIF_CTRL_SPDIFI2S BIT10 202 #define SPDIF_CTRL_MTRIG BIT1 203 #define SPDIF_CTRL_MFFUR BIT0 204 205 /* SPDIF state register (SPDIF_STAT) */ 206 #define SPDIF_STAT_BUSY BIT7 207 #define SPDIF_STAT_FTRIG BIT1 208 #define SPDIF_STAT_FUR BIT0 209 210 #define SPDIF_STAT_FLVL_LSB 8 211 #define SPDIF_STAT_FLVL_MASK BITS_H2L(14, SPDIF_STAT_FLVL_LSB) 212 213 /* SPDIF configure 1 register (SPDIF_CFG1) */ 214 #define SPDIF_CFG1_INITLVL BIT17 215 #define SPDIF_CFG1_ZROVLD BIT16 216 217 #define SPDIF_CFG1_TRIG_LSB 12 218 #define SPDIF_CFG1_TRIG_MASK BITS_H2L(13, SPDIF_CFG1_TRIG_LSB) 219 #define SPDIF_CFG1_TRIG(n) (((n) > 16 ? 3 : (n)/8) << SPDIF_CFG1_TRIG_LSB) /* n = 4, 8, 16, 32 */ 220 221 #define SPDIF_CFG1_SRCNUM_LSB 8 222 #define SPDIF_CFG1_SRCNUM_MASK BITS_H2L(11, SPDIF_CFG1_SRCNUM_LSB) 223 224 #define SPDIF_CFG1_CH1NUM_LSB 4 225 #define SPDIF_CFG1_CH1NUM_MASK BITS_H2L(7, SPDIF_CFG1_CH1NUM_LSB) 226 227 #define SPDIF_CFG1_CH2NUM_LSB 0 228 #define SPDIF_CFG1_CH2NUM_MASK BITS_H2L(3, SPDIF_CFG1_CH2NUM_LSB) 229 230 /* SPDIF configure 2 register (SPDIF_CFG2) */ 231 #define SPDIF_CFG2_MAXWL BIT18 232 #define SPDIF_CFG2_PRE BIT3 233 #define SPDIF_CFG2_COPYN BIT2 234 #define SPDIF_CFG2_AUDION BIT1 235 #define SPDIF_CFG2_CONPRO BIT0 236 237 #define SPDIF_CFG2_FS_LSB 26 238 #define SPDIF_CFG2_FS_MASK BITS_H2L(29, SPDIF_CFG2_FS_LSB) 239 240 #define SPDIF_CFG2_ORGFRQ_LSB 22 241 #define SPDIF_CFG2_ORGFRQ_MASK BITS_H2L(25, SPDIF_CFG2_ORGFRQ_LSB) 242 243 #define SPDIF_CFG2_SAMWL_LSB 19 244 #define SPDIF_CFG2_SAMWL_MASK BITS_H2L(21, SPDIF_CFG2_SAMWL_LSB) 245 246 #define SPDIF_CFG2_CLKACU_LSB 16 247 #define SPDIF_CFG2_CLKACU_MASK BITS_H2L(17, SPDIF_CFG2_CLKACU_LSB) 248 249 #define SPDIF_CFG2_CATCODE_LSB 8 250 #define SPDIF_CFG2_CATCODE_MASK BITS_H2L(15, SPDIF_CFG2_CATCODE_LSB) 251 252 #define SPDIF_CFG2_CHMD_LSB 6 253 #define SPDIF_CFG2_CHMD_MASK BITS_H2L(7, SPDIF_CFG2_CHMD_LSB) 254 255 /* ICDC internal register access control register(RGADW) */ 256 #define ICDC_RGADW_RGWR BIT16 257 258 #define ICDC_RGADW_RGADDR_LSB 8 259 #define ICDC_RGADW_RGADDR_MASK BITS_H2L(14, ICDC_RGADW_RGADDR_LSB) 260 261 #define ICDC_RGADW_RGDIN_LSB 0 262 #define ICDC_RGADW_RGDIN_MASK BITS_H2L(7, ICDC_RGADW_RGDIN_LSB) 263 264 265 /* ICDC internal register data output register (RGDATA)*/ 266 #define ICDC_RGDATA_IRQ BIT8 267 268 #define ICDC_RGDATA_RGDOUT_LSB 0 269 #define ICDC_RGDATA_RGDOUT_MASK BITS_H2L(7, ICDC_RGDATA_RGDOUT_LSB) 270 271 272 #ifndef __MIPS_ASSEMBLER 273 274 275 #define REG_AIC_FR REG32(AIC_FR) 276 #define REG_AIC0_FR REG32(AIC0_FR) 277 #define REG_AIC_CR REG32(AIC_CR) 278 #define REG_AIC_ACCR1 REG32(AIC_ACCR1) 279 #define REG_AIC_ACCR2 REG32(AIC_ACCR2) 280 #define REG_AIC_I2SCR REG32(AIC_I2SCR) 281 #define REG_AIC_SR REG32(AIC_SR) 282 #define REG_AIC_ACSR REG32(AIC_ACSR) 283 #define REG_AIC_I2SSR REG32(AIC_I2SSR) 284 #define REG_AIC_ACCAR REG32(AIC_ACCAR) 285 #define REG_AIC_ACCDR REG32(AIC_ACCDR) 286 #define REG_AIC_ACSAR REG32(AIC_ACSAR) 287 #define REG_AIC_ACSDR REG32(AIC_ACSDR) 288 #define REG_AIC_I2SDIV REG32(AIC_I2SDIV) 289 #define REG_AIC_DR REG32(AIC_DR) 290 291 #define REG_SPDIF_ENA REG32(SPDIF_ENA) 292 #define REG_SPDIF_CTRL REG32(SPDIF_CTRL) 293 #define REG_SPDIF_STATE REG32(SPDIF_STATE) 294 #define REG_SPDIF_CFG1 REG32(SPDIF_CFG1) 295 #define REG_SPDIF_CFG2 REG32(SPDIF_CFG2) 296 #define REG_SPDIF_FIFO REG32(SPDIF_FIFO) 297 298 #define REG_ICDC_RGADW REG32(ICDC_RGADW) 299 #define REG_ICDC_RGDATA REG32(ICDC_RGDATA) 300 301 #if 0 302 #define __aic_enable() ( REG_AIC_FR |= AIC_FR_ENB ) 303 #define __aic_disable() ( REG_AIC_FR &= ~AIC_FR_ENB ) 304 305 #define __aic_select_ac97() ( REG_AIC_FR &= ~AIC_FR_AUSEL ) 306 #define __aic_select_i2s() ( REG_AIC_FR |= AIC_FR_AUSEL ) 307 308 #define __aic_play_zero() ( REG_AIC_FR &= ~AIC_FR_LSMP ) 309 #define __aic_play_lastsample() ( REG_AIC_FR |= AIC_FR_LSMP ) 310 311 #define __i2s_as_master() ( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD ) 312 #define __i2s_as_slave() ( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) ) 313 314 #define jz_aic_ibck_in (CLRREG32(AIC_FR, AIC_FR_IBCKD)) 315 #define jz_aic_ibck_out (SETREG32(AIC_FR, AIC_FR_IBCKD)) 316 317 #define jz_aic_isync_in (CLRREG32(AIC_FR, AIC_FR_ISYNCD)) 318 #define jz_aic_isync_out (SETREG32(AIC_FR, AIC_FR_ISYNCD)) 319 320 #define jz_aic_enable_dmode (SETREG32(AIC_FR, AIC_FR_DMODE)) 321 #define jz_aic_disable_dmode (CLRREG32(AIC_FR, AIC_FR_DMODE)) 322 323 #define __aic_reset_status() ( REG_AIC_FR & AIC_FR_RST ) 324 325 #define __aic_reset() \ 326 do { \ 327 REG_AIC_FR |= AIC_FR_RST; \ 328 } while(0) 329 330 331 #define __aic_set_transmit_trigger(n) \ 332 do { \ 333 REG_AIC_FR &= ~AIC_FR_TFTH_MASK; \ 334 REG_AIC_FR |= ((n) << AIC_FR_TFTH_LSB); \ 335 } while(0) 336 337 #define __aic_set_receive_trigger(n) \ 338 do { \ 339 REG_AIC_FR &= ~AIC_FR_RFTH_MASK; \ 340 REG_AIC_FR |= ((n) << AIC_FR_RFTH_LSB); \ 341 } while(0) 342 343 #define __aic_enable_oldstyle() 344 #define __aic_enable_newstyle() 345 #define __aic_enable_pack16() ( REG_AIC_CR |= AIC_CR_PACK16 ) 346 #define __aic_enable_unpack16() ( REG_AIC_CR &= ~AIC_CR_PACK16) 347 348 #define jz_aic_set_channel(n) \ 349 do { \ 350 switch((n)) { \ 351 case 1: \ 352 case 2: \ 353 case 4: \ 354 case 6: \ 355 case 8: \ 356 CLRREG32(AIC_CR, AIC_CR_CHANNEL_MASK); \ 357 SETREG32(AIC_CR, ((((n) - 1) << 24) & AIC_CR_CHANNEL_MASK)); \ 358 break; \ 359 default: \ 360 printk("invalid aic channel, must be 1, 2, 4, 6, or 8\n"); \ 361 break; \ 362 } \ 363 } while(0) 364 365 /* n = AIC_CR_CHANNEL_MONO,AIC_CR_CHANNEL_STEREO ... */ 366 #define __aic_out_channel_select(n) \ 367 do { \ 368 REG_AIC_CR &= ~AIC_CR_CHANNEL_MASK; \ 369 REG_AIC_CR |= ((n) << AIC_CR_CHANNEL_LSB ); \ 370 } while(0) 371 372 #define __aic_enable_record() ( REG_AIC_CR |= AIC_CR_EREC ) 373 #define __aic_disable_record() ( REG_AIC_CR &= ~AIC_CR_EREC ) 374 #define __aic_enable_replay() ( REG_AIC_CR |= AIC_CR_ERPL ) 375 #define __aic_disable_replay() ( REG_AIC_CR &= ~AIC_CR_ERPL ) 376 #define __aic_enable_loopback() ( REG_AIC_CR |= AIC_CR_ENLBF ) 377 #define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF ) 378 379 #define __aic_flush_tfifo() ( REG_AIC_CR |= AIC_CR_TFLUSH ) 380 #define __aic_unflush_tfifo() ( REG_AIC_CR &= ~AIC_CR_TFLUSH ) 381 #define __aic_flush_rfifo() ( REG_AIC_CR |= AIC_CR_RFLUSH ) 382 #define __aic_unflush_rfifo() ( REG_AIC_CR &= ~AIC_CR_RFLUSH ) 383 384 #define __aic_enable_transmit_intr() \ 385 ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) ) 386 #define __aic_disable_transmit_intr() \ 387 ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) ) 388 #define __aic_enable_receive_intr() \ 389 ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) ) 390 #define __aic_disable_receive_intr() \ 391 ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) ) 392 393 #define __aic_enable_transmit_dma() ( REG_AIC_CR |= AIC_CR_TDMS ) 394 #define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS ) 395 #define __aic_enable_receive_dma() ( REG_AIC_CR |= AIC_CR_RDMS ) 396 #define __aic_disable_receive_dma() ( REG_AIC_CR &= ~AIC_CR_RDMS ) 397 398 #define __aic_enable_mono2stereo() ( REG_AIC_CR |= AIC_CR_M2S ) 399 #define __aic_disable_mono2stereo() ( REG_AIC_CR &= ~AIC_CR_M2S ) 400 #define __aic_enable_byteswap() ( REG_AIC_CR |= AIC_CR_ENDSW ) 401 #define __aic_disable_byteswap() ( REG_AIC_CR &= ~AIC_CR_ENDSW ) 402 #define __aic_enable_unsignadj() ( REG_AIC_CR |= AIC_CR_AVSTSU ) 403 #define __aic_disable_unsignadj() ( REG_AIC_CR &= ~AIC_CR_AVSTSU ) 404 405 #define AC97_PCM_XS_L_FRONT AIC_ACCR1_XS_SLOT(3) 406 #define AC97_PCM_XS_R_FRONT AIC_ACCR1_XS_SLOT(4) 407 #define AC97_PCM_XS_CENTER AIC_ACCR1_XS_SLOT(6) 408 #define AC97_PCM_XS_L_SURR AIC_ACCR1_XS_SLOT(7) 409 #define AC97_PCM_XS_R_SURR AIC_ACCR1_XS_SLOT(8) 410 #define AC97_PCM_XS_LFE AIC_ACCR1_XS_SLOT(9) 411 412 #define AC97_PCM_RS_L_FRONT AIC_ACCR1_RS_SLOT(3) 413 #define AC97_PCM_RS_R_FRONT AIC_ACCR1_RS_SLOT(4) 414 #define AC97_PCM_RS_CENTER AIC_ACCR1_RS_SLOT(6) 415 #define AC97_PCM_RS_L_SURR AIC_ACCR1_RS_SLOT(7) 416 #define AC97_PCM_RS_R_SURR AIC_ACCR1_RS_SLOT(8) 417 #define AC97_PCM_RS_LFE AIC_ACCR1_RS_SLOT(9) 418 419 #define __ac97_set_xs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK ) 420 #define __ac97_set_xs_mono() \ 421 do { \ 422 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ 423 REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT; \ 424 } while(0) 425 #define __ac97_set_xs_stereo() \ 426 do { \ 427 REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK; \ 428 REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT; \ 429 } while(0) 430 431 /* In fact, only stereo is support now. */ 432 #define __ac97_set_rs_none() ( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK ) 433 #define __ac97_set_rs_mono() \ 434 do { \ 435 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ 436 REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT; \ 437 } while(0) 438 #define __ac97_set_rs_stereo() \ 439 do { \ 440 REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK; \ 441 REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT; \ 442 } while(0) 443 444 #define __ac97_warm_reset_codec() \ 445 do { \ 446 REG_AIC_ACCR2 |= AIC_ACCR2_SA; \ 447 REG_AIC_ACCR2 |= AIC_ACCR2_SS; \ 448 udelay(2); \ 449 REG_AIC_ACCR2 &= ~AIC_ACCR2_SS; \ 450 REG_AIC_ACCR2 &= ~AIC_ACCR2_SA; \ 451 } while (0) 452 453 #define __ac97_cold_reset_codec() \ 454 do { \ 455 REG_AIC_ACCR2 |= AIC_ACCR2_SR; \ 456 udelay(2); \ 457 REG_AIC_ACCR2 &= ~AIC_ACCR2_SR; \ 458 } while (0) 459 460 /* n=8,16,18,20 */ 461 #define __ac97_set_iass(n) \ 462 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT ) 463 #define __ac97_set_oass(n) \ 464 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT ) 465 466 /* This bit should only be set in 2 channels configuration */ 467 #define __i2s_send_rfirst() ( REG_AIC_I2SCR |= AIC_I2SCR_RFIRST ) /* RL */ 468 #define __i2s_send_lfirst() ( REG_AIC_I2SCR &= ~AIC_I2SCR_RFIRST ) /* LR */ 469 470 /* This bit should only be set in 2 channels configuration and 16bit-packed mode */ 471 #define __i2s_switch_lr() ( REG_AIC_I2SCR |= AIC_I2SCR_SWLH ) 472 #define __i2s_unswitch_lr() ( REG_AIC_I2SCR &= ~AIC_I2SCR_SWLH ) 473 474 #define __i2s_select_i2s() ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL ) 475 #define __i2s_select_msbjustified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL ) 476 477 /* n=8,16,18,20,24 */ 478 /*#define __i2s_set_sample_size(n) \ 479 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )*/ 480 481 #define __i2s_out_channel_select(n) __aic_out_channel_select(n) 482 483 #define __i2s_set_oss_sample_size(n) \ 484 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_OSS_MASK) | AIC_CR_OSS(n)) 485 #define __i2s_set_iss_sample_size(n) \ 486 ( REG_AIC_CR = (REG_AIC_CR & ~AIC_CR_ISS_MASK) | AIC_CR_ISS(n)) 487 488 #define __i2s_stop_bitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK ) 489 #define __i2s_start_bitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK ) 490 491 #define __i2s_stop_ibitclk() ( REG_AIC_I2SCR |= AIC_I2SCR_ISTPBK ) 492 #define __i2s_start_ibitclk() ( REG_AIC_I2SCR &= ~AIC_I2SCR_ISTPBK ) 493 494 #define __aic_transmit_request() ( REG_AIC_SR & AIC_SR_TFS ) 495 #define __aic_receive_request() ( REG_AIC_SR & AIC_SR_RFS ) 496 #define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR ) 497 #define __aic_receive_overrun() ( REG_AIC_SR & AIC_SR_ROR ) 498 499 #define __aic_clear_errors() ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) ) 500 501 #define __aic_get_transmit_resident() \ 502 ( (REG_AIC_SR & AIC_SR_TFL_MASK) >> AIC_SR_TFL_LSB ) 503 #define __aic_get_receive_count() \ 504 ( (REG_AIC_SR & AIC_SR_RFL_MASK) >> AIC_SR_RFL_LSB ) 505 506 #define __ac97_command_transmitted() ( REG_AIC_ACSR & AIC_ACSR_CADT ) 507 #define __ac97_status_received() ( REG_AIC_ACSR & AIC_ACSR_SADR ) 508 #define __ac97_status_receive_timeout() ( REG_AIC_ACSR & AIC_ACSR_RSTO ) 509 #define __ac97_codec_is_low_power_mode() ( REG_AIC_ACSR & AIC_ACSR_CLPM ) 510 #define __ac97_codec_is_ready() ( REG_AIC_ACSR & AIC_ACSR_CRDY ) 511 #define __ac97_slot_error_detected() ( REG_AIC_ACSR & AIC_ACSR_SLTERR ) 512 #define __ac97_clear_slot_error() ( REG_AIC_ACSR &= ~AIC_ACSR_SLTERR ) 513 514 #define __i2s_is_busy() ( REG_AIC_I2SSR & AIC_I2SSR_BSY ) 515 516 #define __ac97_out_rcmd_addr(reg) \ 517 do { \ 518 REG_AIC_ACCAR = AC97_READ_CMD | ((reg) << AC97_INDEX_LSB); \ 519 } while (0) 520 521 #define __ac97_out_wcmd_addr(reg) \ 522 do { \ 523 REG_AIC_ACCAR = AC97_WRITE_CMD | ((reg) << AC97_INDEX_LSB); \ 524 } while (0) 525 526 #define __ac97_out_data(value) \ 527 do { \ 528 REG_AIC_ACCDR = ((value) << AC97_DATA_LSB); \ 529 } while (0) 530 531 #define __ac97_in_data() \ 532 ( (REG_AIC_ACSDR & CODEC_REG_DATA_MASK) >> AC97_DATA_LSB ) 533 534 #define __ac97_in_status_addr() \ 535 ( (REG_AIC_ACSAR & AC97_INDEX_MASK) >> AC97_INDEX_LSB ) 536 537 #define __i2s_set_sample_rate(i2sclk, sync) \ 538 ( REG_AIC_I2SDIV = ((i2sclk) / (4*64)) / (sync) ) 539 540 #define __aic_write_tfifo(v) ( REG_AIC_DR = (v) ) 541 #define __aic_read_rfifo() ( REG_AIC_DR ) 542 543 #define __aic_internal_codec() ( REG_AIC_FR |= AIC_FR_ICDC ) 544 #define __aic_external_codec() ( REG_AIC_FR &= ~AIC_FR_ICDC ) 545 #define __aic0_internal_codec() ( REG_AIC0_FR |= AIC_FR_ICDC ) 546 #define __aic0_external_codec() ( REG_AIC0_FR &= ~AIC_FR_ICDC ) 547 548 // 549 // Define next ops for AC97 compatible 550 // 551 552 #define AC97_ACSR AIC_ACSR 553 554 #define __ac97_enable() __aic_enable(); __aic_select_ac97() 555 #define __ac97_disable() __aic_disable() 556 #define __ac97_reset() __aic_reset() 557 558 #define __ac97_set_transmit_trigger(n) __aic_set_transmit_trigger(n) 559 #define __ac97_set_receive_trigger(n) __aic_set_receive_trigger(n) 560 561 #define __ac97_enable_record() __aic_enable_record() 562 #define __ac97_disable_record() __aic_disable_record() 563 #define __ac97_enable_replay() __aic_enable_replay() 564 #define __ac97_disable_replay() __aic_disable_replay() 565 #define __ac97_enable_loopback() __aic_enable_loopback() 566 #define __ac97_disable_loopback() __aic_disable_loopback() 567 568 #define __ac97_enable_transmit_dma() __aic_enable_transmit_dma() 569 #define __ac97_disable_transmit_dma() __aic_disable_transmit_dma() 570 #define __ac97_enable_receive_dma() __aic_enable_receive_dma() 571 #define __ac97_disable_receive_dma() __aic_disable_receive_dma() 572 573 #define __ac97_transmit_request() __aic_transmit_request() 574 #define __ac97_receive_request() __aic_receive_request() 575 #define __ac97_transmit_underrun() __aic_transmit_underrun() 576 #define __ac97_receive_overrun() __aic_receive_overrun() 577 578 #define __ac97_clear_errors() __aic_clear_errors() 579 580 #define __ac97_get_transmit_resident() __aic_get_transmit_resident() 581 #define __ac97_get_receive_count() __aic_get_receive_count() 582 583 #define __ac97_enable_transmit_intr() __aic_enable_transmit_intr() 584 #define __ac97_disable_transmit_intr() __aic_disable_transmit_intr() 585 #define __ac97_enable_receive_intr() __aic_enable_receive_intr() 586 #define __ac97_disable_receive_intr() __aic_disable_receive_intr() 587 588 #define __ac97_write_tfifo(v) __aic_write_tfifo(v) 589 #define __ac97_read_rfifo() __aic_read_rfifo() 590 591 // 592 // Define next ops for I2S compatible 593 // 594 595 #define I2S_ACSR AIC_I2SSR 596 597 #define __i2s_enable() __aic_enable(); __aic_select_i2s() 598 #define __i2s_disable() __aic_disable() 599 #define __i2s_reset() __aic_reset() 600 601 #define __i2s_set_transmit_trigger(n) __aic_set_transmit_trigger(n) 602 #define __i2s_set_receive_trigger(n) __aic_set_receive_trigger(n) 603 604 #define __i2s_enable_record() __aic_enable_record() 605 #define __i2s_disable_record() __aic_disable_record() 606 #define __i2s_enable_replay() __aic_enable_replay() 607 #define __i2s_disable_replay() __aic_disable_replay() 608 #define __i2s_enable_loopback() __aic_enable_loopback() 609 #define __i2s_disable_loopback() __aic_disable_loopback() 610 611 #define __i2s_enable_transmit_dma() __aic_enable_transmit_dma() 612 #define __i2s_disable_transmit_dma() __aic_disable_transmit_dma() 613 #define __i2s_enable_receive_dma() __aic_enable_receive_dma() 614 #define __i2s_disable_receive_dma() __aic_disable_receive_dma() 615 616 #define __i2s_transmit_request() __aic_transmit_request() 617 #define __i2s_receive_request() __aic_receive_request() 618 #define __i2s_transmit_underrun() __aic_transmit_underrun() 619 #define __i2s_receive_overrun() __aic_receive_overrun() 620 621 #define __i2s_clear_errors() __aic_clear_errors() 622 623 #define __i2s_get_transmit_resident() __aic_get_transmit_resident() 624 #define __i2s_get_receive_count() __aic_get_receive_count() 625 626 #define __i2s_enable_transmit_intr() __aic_enable_transmit_intr() 627 #define __i2s_disable_transmit_intr() __aic_disable_transmit_intr() 628 #define __i2s_enable_receive_intr() __aic_enable_receive_intr() 629 #define __i2s_disable_receive_intr() __aic_disable_receive_intr() 630 631 #define __i2s_write_tfifo(v) __aic_write_tfifo(v) 632 #define __i2s_read_rfifo() __aic_read_rfifo() 633 634 #define __i2s_reset_codec() \ 635 do { \ 636 } while (0) 637 638 639 /************************************************************************* 640 * SPDIF INTERFACE in AIC Controller 641 *************************************************************************/ 642 643 #define __spdif_enable() ( REG_SPDIF_ENA |= SPDIF_ENA_SPEN ) 644 #define __spdif_disable() ( REG_SPDIF_ENA &= ~SPDIF_ENA_SPEN ) 645 646 #define __spdif_enable_transmit_dma() ( REG_SPDIF_CTRL |= SPDIF_CTRL_DMAEN ) 647 #define __spdif_disable_transmit_dma() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DMAEN ) 648 #define __spdif_enable_dtype() ( REG_SPDIF_CTRL |= SPDIF_CTRL_DTYPE ) 649 #define __spdif_disable_dtype() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_DTYPE ) 650 #define __spdif_enable_sign() ( REG_SPDIF_CTRL |= SPDIF_CTRL_SIGN ) 651 #define __spdif_disable_sign() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SIGN ) 652 #define __spdif_enable_invalid() ( REG_SPDIF_CTRL |= SPDIF_CTRL_INVALID ) 653 #define __spdif_disable_invalid() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_INVALID ) 654 #define __spdif_enable_reset() ( REG_SPDIF_CTRL |= SPDIF_CTRL_RST ) 655 #define __spdif_select_spdif() ( REG_SPDIF_CTRL |= SPDIF_CTRL_SPDIFI2S ) 656 #define __spdif_select_i2s() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_SPDIFI2S ) 657 #define __spdif_enable_MTRIGmask() ( REG_SPDIF_CTRL |= SPDIF_CTRL_MTRIG ) 658 #define __spdif_disable_MTRIGmask() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MTRIG ) 659 #define __spdif_enable_MFFURmask() ( REG_SPDIF_CTRL |= SPDIF_CTRL_MFFUR ) 660 #define __spdif_disable_MFFURmask() ( REG_SPDIF_CTRL &= ~SPDIF_CTRL_MFFUR ) 661 662 #define __spdif_enable_initlvl_high() ( REG_SPDIF_CFG1 |= SPDIF_CFG1_INITLVL ) 663 #define __spdif_enable_initlvl_low() ( REG_SPDIF_CFG1 &= ~SPDIF_CFG1_INITLVL ) 664 #define __spdif_enable_zrovld_invald() ( REG_SPDIF_CFG1 |= SPDIF_CFG1_ZROVLD ) 665 #define __spdif_enable_zrovld_vald() ( REG_SPDIF_CFG1 &= ~SPDIF_CFG1_ZROVLD ) 666 667 /* 0, 1, 2, 3 */ 668 #define __spdif_set_transmit_trigger(n) \ 669 do { \ 670 REG_SPDIF_CFG1 &= ~SPDIF_CFG1_TRIG_MASK; \ 671 REG_SPDIF_CFG1 |= SPDIF_CFG1_TRIG(n); \ 672 } while(0) 673 674 /* 1 ~ 15 */ 675 #define __spdif_set_srcnum(n) \ 676 do { \ 677 REG_SPDIF_CFG1 &= ~SPDIF_CFG1_SRCNUM_MASK; \ 678 REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_SRCNUM_LSB); \ 679 } while(0) 680 681 /* 1 ~ 15 */ 682 #define __spdif_set_ch1num(n) \ 683 do { \ 684 REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH1NUM_MASK; \ 685 REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH1NUM_LSB); \ 686 } while(0) 687 688 /* 1 ~ 15 */ 689 #define __spdif_set_ch2num(n) \ 690 do { \ 691 REG_SPDIF_CFG1 &= ~SPDIF_CFG1_CH2NUM_MASK; \ 692 REG_SPDIF_CFG1 |= ((n) << SPDIF_CFG1_CH2NUM_LSB); \ 693 } while(0) 694 695 /* 0x0, 0x2, 0x3, 0xa, 0xe */ 696 #define __spdif_set_fs(n) \ 697 do { \ 698 REG_SPDIF_CFG2 &= ~SPDIF_CFG2_FS_MASK; \ 699 REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_FS_LSB); \ 700 } while(0) 701 702 /* 0xd, 0xc, 0x5, 0x1 */ 703 #define __spdif_set_orgfrq(n) \ 704 do { \ 705 REG_SPDIF_CFG2 &= ~SPDIF_CFG2_ORGFRQ_MASK; \ 706 REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_ORGFRQ_LSB); \ 707 } while(0) 708 709 /* 0x1, 0x6, 0x2, 0x4, 0x5 */ 710 #define __spdif_set_samwl(n) \ 711 do { \ 712 REG_SPDIF_CFG2 &= ~SPDIF_CFG2_SAMWL_MASK; \ 713 REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_SAMWL_LSB); \ 714 } while(0) 715 716 #define __spdif_enable_samwl_24() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_MAXWL ) 717 #define __spdif_enable_samwl_20() ( REG_SPDIF_CFG1 &= ~SPDIF_CFG2_MAXWL ) 718 719 /* 0x1, 0x1, 0x2, 0x3 */ 720 #define __spdif_set_clkacu(n) \ 721 do { \ 722 REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CLKACU_MASK; \ 723 REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CLKACU_LSB); \ 724 } while(0) 725 726 /* see IEC60958-3 */ 727 #define __spdif_set_catcode(n) \ 728 do { \ 729 REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CATCODE_MASK; \ 730 REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CATCODE_LSB); \ 731 } while(0) 732 733 /* n = 0x0, */ 734 #define __spdif_set_chmode(n) \ 735 do { \ 736 REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CHMD_MASK; \ 737 REG_SPDIF_CFG2 |= ((n) << SPDIF_CFG2_CHMD_LSB); \ 738 } while(0) 739 740 #define __spdif_enable_pre() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_PRE ) 741 #define __spdif_disable_pre() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_PRE ) 742 #define __spdif_enable_copyn() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_COPYN ) 743 #define __spdif_disable_copyn() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_COPYN ) 744 /* audio sample word represents linear PCM samples */ 745 #define __spdif_enable_audion() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_AUDION ) 746 /* udio sample word used for other purpose */ 747 #define __spdif_disable_audion() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_AUDION ) 748 #define __spdif_enable_conpro() ( REG_SPDIF_CFG2 &= ~SPDIF_CFG2_CONPRO ) 749 #define __spdif_disable_conpro() ( REG_SPDIF_CFG2 |= SPDIF_CFG2_CONPRO ) 750 751 /*************************************************************************** 752 * ICDC 753 ***************************************************************************/ 754 #define __i2s_internal_codec() __aic_internal_codec() 755 #define __i2s_external_codec() __aic_external_codec() 756 757 #define __icdc_clk_ready() ( REG_ICDC_CKCFG & ICDC_CKCFG_CKRDY ) 758 #define __icdc_sel_adc() ( REG_ICDC_CKCFG |= ICDC_CKCFG_SELAD ) 759 #define __icdc_sel_dac() ( REG_ICDC_CKCFG &= ~ICDC_CKCFG_SELAD ) 760 761 #define __icdc_set_rgwr() ( REG_ICDC_RGADW |= ICDC_RGADW_RGWR ) 762 #define __icdc_clear_rgwr() ( REG_ICDC_RGADW &= ~ICDC_RGADW_RGWR ) 763 #define __icdc_rgwr_ready() ( REG_ICDC_RGADW & ICDC_RGADW_RGWR ) 764 765 #define AIC_RW_CODEC_START() while (INREG32(ICDC_RGADW) & ICDC_RGADW_RGWR) 766 #define AIC_RW_CODEC_STOP() while (INREG32(ICDC_RGADW) & ICDC_RGADW_RGWR) 767 768 769 #define __icdc_set_addr(n) \ 770 do { \ 771 REG_ICDC_RGADW &= ~ICDC_RGADW_RGADDR_MASK; \ 772 REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGADDR_LSB; \ 773 } while(0) 774 775 #define __icdc_set_cmd(n) \ 776 do { \ 777 REG_ICDC_RGADW &= ~ICDC_RGADW_RGDIN_MASK; \ 778 REG_ICDC_RGADW |= (n) << ICDC_RGADW_RGDIN_LSB; \ 779 } while(0) 780 781 #define __icdc_irq_pending() ( REG_ICDC_RGDATA & ICDC_RGDATA_IRQ ) 782 #define __icdc_get_value() ( REG_ICDC_RGDATA & ICDC_RGDATA_RGDOUT_MASK ) 783 784 785 786 #endif /* __MIPS_ASSEMBLER */ 787 788 #endif 789 790 #ifdef __cplusplus 791 } 792 #endif 793 794 #endif /* _X1000_AIC_H_ */ 795