Lines Matching full:divider
129 CLKDIVN_OFS EQU 0x14 ; Clock Divider Control Register Offset
130 CAMDIVN_OFS EQU 0x18 ; Camera Clock Divider Register Offset
139 ;// <o2.12..19> m: Main Divider m Value <9-256><#-8>
141 ;// <o2.4..9> p: Pre-divider p Value <3-64><#-2>
143 ;// <o2.0..1> s: Post Divider s Value <0-3>
148 ;// <o3.12..19> m: Main Divider m Value <8-263><#-8>
150 ;// <o3.4..9> p: Pre-divider p Value <2-65><#-2>
152 ;// <o3.0..1> s: Post Divider s Value <0-3>
180 ;// <o5.0..2> SLOW_VAL: Slow Clock Divider <0-7>
182 ;// <h> Clock Divider Control Register (CLKDIVN)
195 ;// <h> Camera Clock Divider Control Register (CAMDIVN)
208 ;// <o7.0..3> CAMCLK_DIV: CAMCLK Divider <0-15>
210 ;// <i> Divider is used only if CAMCLK_SEL = 1