Tool: cancel DIP-C write when in FPGA (#2009)

* constant variable: add FPAGPlatform parameter

* scripts: set WITH_CONSTANTIN to 1 by default

* submodules: version to lyq repository for test

Tool: cancel DIP-C write when in FPGA (#2009)

* constant variable: add FPAGPlatform parameter

* scripts: set WITH_CONSTANTIN to 1 by default

* submodules: version to lyq repository for test

* Revert "constant variable: add FPAGPlatform parameter"

This reverts commit fc2f03b768cb2ad63cb543096b00b971c85467d6.

* constant: add FPGA init

* chiseldb: add FPGA init

* difftest: version

* chisledb: add envFPGA situation

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util: change ElaborationArtefacts to FileRegisters (#1973)

* util: change ElaborationArtefacts to FileRegisters

use `filename` instead of `extension` to record file

* huancun: merge master

util: change ElaborationArtefacts to FileRegisters (#1973)

* util: change ElaborationArtefacts to FileRegisters

use `filename` instead of `extension` to record file

* huancun: merge master

* huancun: version change

* util: update to main

* SimTop: delete unused comment

* constantin: fix bug which reduced emputy map

* code opt: add write api in FileRegisters

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SimTop: add support for Constantin

Switch to asynchronous reset for all modules (#1867)

This commit changes the reset of all modules to asynchronous style,
including changes on the initialization values of some registers.
For async

Switch to asynchronous reset for all modules (#1867)

This commit changes the reset of all modules to asynchronous style,
including changes on the initialization values of some registers.
For async registers, they must have constant reset values.

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Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

sim: add AXI4 memory slave model in Chisel (#1799)

Added chisel-db to dump hw data into a database automatically

soc: fix implementation of rtc_clock (#1565)

Previously we made a mistake to connect rtc_clock to rtcTick for CLINT.

rtcTick should be on io_clock clock domain and asserted only one
clock cycle

soc: fix implementation of rtc_clock (#1565)

Previously we made a mistake to connect rtc_clock to rtcTick for CLINT.

rtcTick should be on io_clock clock domain and asserted only one
clock cycle in io_clock for every cycle in rtc_clock. We add sampling
registers in this commit to fix this.

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top: add real-time clock for CLINT (#1553)

pass reset vector from SimTop (#1545)

Misc: add support for compiling with CIRCT

bump difftest and fix Makefile for VCS support

DTS: add interrupt-controller into cpu (#1298)

Add pma checker for I/O device (#1300)

* SoC: add axi4spliter

* pmp: add apply method to reduce loc

* pma: add PMA used in axi4's spliter

* Fix package import

* pma: re-write tl-pma, put

Add pma checker for I/O device (#1300)

* SoC: add axi4spliter

* pmp: add apply method to reduce loc

* pma: add PMA used in axi4's spliter

* Fix package import

* pma: re-write tl-pma, put tl-pma into AXI4Spliter

* pma: add memory mapped pma

* soc: rm dma port, rm axi4spliter, mv mmpma out of spliter

* Remove unused files

* update dma pma check port at SimTop.scala; update pll lock defalt value to 1

Co-authored-by: ZhangZifei <[email protected]>
Co-authored-by: rvcoresjw <[email protected]>

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top: enable fpga option for simulation emu (#1213)

* disable log as default
* code clean up

Refactor config & Add pll (#1181)

* Add cache ctrl node

* L2/L3: Reduce client dir size

* Ctrl: connect soft reset from L3 to core

* Add pll

* Config: seperate SocParams and CoreParams t

Refactor config & Add pll (#1181)

* Add cache ctrl node

* L2/L3: Reduce client dir size

* Ctrl: connect soft reset from L3 to core

* Add pll

* Config: seperate SocParams and CoreParams to get correct number of cores

* Bump huancun

* Add pll output

* Fix inclusive cache config

* Add one more pll ctrl reg

* Bump huancun

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top: remove osc_clock and pll_output

misc: put reset signals in a chain (#1147)

Refactor top (#1093)

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Refactor Top

* Bump huancun

* alu: fix bug of rev8 & orc.b instruction

Co-authored-by: Zhang

Refactor top (#1093)

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Refactor Top

* Bump huancun

* alu: fix bug of rev8 & orc.b instruction

Co-authored-by: Zhangfw <[email protected]>

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Temporarily disable TLMonitor (#1087)

modify dma bus width form 256 to 128 bits (#1041)

* add top IOs

* modify dma bus data width from 256 to 128 bits

* add top single to SimTop.scala

fudian: The new floating-point lib to replace hardfloat (#975)

* Add submodule 'fudian'

* IntToFP: use fudian

* FMA: use fudian.CMA

* FPToInt: remove recode format

Bump chisel to 3.5 (#974)

* bump chisel to 3.5

* Remove deprecated 'toBool' && disable tl monitor

* Update RocketChip / Re-enable TLMonitor

* Makefile: remove '--infer-rw'

core: add basic debug mode features (#918)

Basic features of debug mode are implemented.

* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support

core: add basic debug mode features (#918)

Basic features of debug mode are implemented.

* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support
* Use difftest with JTAG support

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Update difftest to use NEMU master branch (#902)

misc: implement difftest as a submodule