1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import chisel3.stage.ChiselGeneratorAnnotation 23import device.{AXI4RAMWrapper, SimJTAG} 24import difftest._ 25import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule} 26import freechips.rocketchip.util.ElaborationArtefacts 27import top.TopMain.writeOutputFile 28import utils.GTimer 29import xiangshan.DebugOptionsKey 30 31class SimTop(implicit p: Parameters) extends Module { 32 val debugOpts = p(DebugOptionsKey) 33 val useDRAMSim = debugOpts.UseDRAMSim 34 35 val l_soc = LazyModule(new XSTop()) 36 val soc = Module(l_soc.module) 37 // Don't allow the top-level signals to be optimized out, 38 // so that we can re-use this SimTop for any generated Verilog RTL. 39 dontTouch(soc.io) 40 41 l_soc.module.dma <> 0.U.asTypeOf(l_soc.module.dma) 42 43 val l_simMMIO = LazyModule(new SimMMIO(l_soc.misc.peripheralNode.in.head._2)) 44 val simMMIO = Module(l_simMMIO.module) 45 l_simMMIO.io_axi4 <> soc.peripheral 46 47 if(!useDRAMSim){ 48 val l_simAXIMem = LazyModule(new AXI4RAMWrapper( 49 l_soc.misc.memAXI4SlaveNode, 8L * 1024 * 1024 * 1024, useBlackBox = true 50 )) 51 val simAXIMem = Module(l_simAXIMem.module) 52 l_simAXIMem.io_axi4 <> soc.memory 53 } 54 55 soc.io.clock := clock.asBool 56 soc.io.reset := reset.asBool 57 soc.io.extIntrs := simMMIO.io.interrupt.intrVec 58 soc.io.sram_config := 0.U 59 soc.io.pll0_lock := true.B 60 soc.io.cacheable_check := DontCare 61 soc.io.riscv_rst_vec.foreach(_ := 0x10000000L.U) 62 63 // soc.io.rtc_clock is a div100 of soc.io.clock 64 val rtcClockDiv = 100 65 val rtcTickCycle = rtcClockDiv / 2 66 val rtcCounter = RegInit(0.U(log2Ceil(rtcTickCycle + 1).W)) 67 rtcCounter := Mux(rtcCounter === (rtcTickCycle - 1).U, 0.U, rtcCounter + 1.U) 68 val rtcClock = RegInit(false.B) 69 when (rtcCounter === 0.U) { 70 rtcClock := ~rtcClock 71 } 72 soc.io.rtc_clock := rtcClock 73 74 val success = Wire(Bool()) 75 val jtag = Module(new SimJTAG(tickDelay=3)(p)).connect(soc.io.systemjtag.jtag, clock, reset.asBool, !reset.asBool, success) 76 soc.io.systemjtag.reset := reset 77 soc.io.systemjtag.mfr_id := 0.U(11.W) 78 soc.io.systemjtag.part_number := 0.U(16.W) 79 soc.io.systemjtag.version := 0.U(4.W) 80 81 val io = IO(new Bundle(){ 82 val logCtrl = new LogCtrlIO 83 val perfInfo = new PerfInfoIO 84 val uart = new UARTIO 85 val memAXI = if(useDRAMSim) soc.memory.cloneType else null 86 }) 87 88 simMMIO.io.uart <> io.uart 89 90 if(useDRAMSim){ 91 io.memAXI <> soc.memory 92 } 93 94 if (!debugOpts.FPGAPlatform && (debugOpts.EnableDebug || debugOpts.EnablePerfDebug)) { 95 val timer = GTimer() 96 val logEnable = (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end) 97 ExcitingUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE") 98 ExcitingUtils.addSource(timer, "logTimestamp") 99 } 100 101 if (!debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug) { 102 val clean = io.perfInfo.clean 103 val dump = io.perfInfo.dump 104 ExcitingUtils.addSource(clean, "XSPERF_CLEAN") 105 ExcitingUtils.addSource(dump, "XSPERF_DUMP") 106 } 107 108 // Check and dispaly all source and sink connections 109 ExcitingUtils.fixConnections() 110 ExcitingUtils.checkAndDisplay() 111} 112 113object SimTop extends App { 114 override def main(args: Array[String]): Unit = { 115 // Keep this the same as TopMain except that SimTop is used here instead of XSTop 116 val (config, firrtlOpts, firrtlComplier) = ArgParser.parse(args) 117 Generator.execute( 118 firrtlOpts, 119 DisableMonitors(p => new SimTop()(p))(config), 120 firrtlComplier 121 ) 122 ElaborationArtefacts.files.foreach{ case (extension, contents) => 123 writeOutputFile("./build", s"XSTop.${extension}", contents()) 124 } 125 } 126} 127