1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chipsalliance.rocketchip.config.{Config, Parameters} 20import chisel3.stage.ChiselGeneratorAnnotation 21import chisel3._ 22import device.{AXI4RAMWrapper, SimJTAG} 23import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule, LazyModuleImp} 24import utils.GTimer 25import xiangshan.{DebugOptions, DebugOptionsKey} 26import chipsalliance.rocketchip.config._ 27import freechips.rocketchip.devices.debug._ 28import difftest._ 29import freechips.rocketchip.util.ElaborationArtefacts 30import top.TopMain.writeOutputFile 31 32class SimTop(implicit p: Parameters) extends Module { 33 val debugOpts = p(DebugOptionsKey) 34 val useDRAMSim = debugOpts.UseDRAMSim 35 36 val l_soc = LazyModule(new XSTop()) 37 val soc = Module(l_soc.module) 38 // Don't allow the top-level signals to be optimized out, 39 // so that we can re-use this SimTop for any generated Verilog RTL. 40 dontTouch(soc.io) 41 42 l_soc.module.dma <> 0.U.asTypeOf(l_soc.module.dma) 43 44 val l_simMMIO = LazyModule(new SimMMIO(l_soc.misc.peripheralNode.in.head._2)) 45 val simMMIO = Module(l_simMMIO.module) 46 l_simMMIO.io_axi4 <> soc.peripheral 47 48 if(!useDRAMSim){ 49 val l_simAXIMem = LazyModule(new AXI4RAMWrapper( 50 l_soc.misc.memAXI4SlaveNode, 8L * 1024 * 1024 * 1024, useBlackBox = true 51 )) 52 val simAXIMem = Module(l_simAXIMem.module) 53 l_simAXIMem.io_axi4 <> soc.memory 54 } 55 56 soc.io.clock := clock.asBool 57 soc.io.reset := reset.asBool 58 soc.io.extIntrs := simMMIO.io.interrupt.intrVec 59 soc.io.sram_config := 0.U 60 soc.io.pll0_lock := true.B 61 soc.io.cacheable_check := DontCare 62 soc.io.riscv_rst_vec.foreach(_ := 0x10000000L.U) 63 val rtcClockDiv = 100 64 val rtcCounter = RegInit(0.U) 65 rtcCounter := Mux(rtcCounter === (rtcClockDiv - 1).U, 0.U, rtcCounter + 1.U) 66 soc.io.rtc_clock := rtcCounter === 0.U 67 68 val success = Wire(Bool()) 69 val jtag = Module(new SimJTAG(tickDelay=3)(p)).connect(soc.io.systemjtag.jtag, clock, reset.asBool, !reset.asBool, success) 70 soc.io.systemjtag.reset := reset 71 soc.io.systemjtag.mfr_id := 0.U(11.W) 72 soc.io.systemjtag.part_number := 0.U(16.W) 73 soc.io.systemjtag.version := 0.U(4.W) 74 75 val io = IO(new Bundle(){ 76 val logCtrl = new LogCtrlIO 77 val perfInfo = new PerfInfoIO 78 val uart = new UARTIO 79 val memAXI = if(useDRAMSim) soc.memory.cloneType else null 80 }) 81 82 simMMIO.io.uart <> io.uart 83 84 if(useDRAMSim){ 85 io.memAXI <> soc.memory 86 } 87 88 if (!debugOpts.FPGAPlatform && (debugOpts.EnableDebug || debugOpts.EnablePerfDebug)) { 89 val timer = GTimer() 90 val logEnable = (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end) 91 ExcitingUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE") 92 ExcitingUtils.addSource(timer, "logTimestamp") 93 } 94 95 if (!debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug) { 96 val clean = io.perfInfo.clean 97 val dump = io.perfInfo.dump 98 ExcitingUtils.addSource(clean, "XSPERF_CLEAN") 99 ExcitingUtils.addSource(dump, "XSPERF_DUMP") 100 } 101 102 // Check and dispaly all source and sink connections 103 ExcitingUtils.fixConnections() 104 ExcitingUtils.checkAndDisplay() 105} 106 107object SimTop extends App { 108 override def main(args: Array[String]): Unit = { 109 // Keep this the same as TopMain except that SimTop is used here instead of XSTop 110 val (config, firrtlOpts, firrtlComplier) = ArgParser.parse(args) 111 Generator.execute( 112 firrtlOpts, 113 DisableMonitors(p => new SimTop()(p))(config), 114 firrtlComplier 115 ) 116 ElaborationArtefacts.files.foreach{ case (extension, contents) => 117 writeOutputFile("./build", s"XSTop.${extension}", contents()) 118 } 119 } 120} 121