xref: /XiangShan/src/test/scala/top/SimTop.scala (revision 3a62c537bdeb2b9f549dbcdeb92a60bd87df642f) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chipsalliance.rocketchip.config.{Config, Parameters}
20import chisel3.stage.ChiselGeneratorAnnotation
21import chisel3._
22import device.{AXI4RAMWrapper, SimJTAG}
23import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule, LazyModuleImp}
24import utils.GTimer
25import xiangshan.{DebugOptions, DebugOptionsKey}
26import chipsalliance.rocketchip.config._
27import freechips.rocketchip.devices.debug._
28import difftest._
29import freechips.rocketchip.util.ElaborationArtefacts
30import top.TopMain.writeOutputFile
31
32class SimTop(implicit p: Parameters) extends Module {
33  val debugOpts = p(DebugOptionsKey)
34  val useDRAMSim = debugOpts.UseDRAMSim
35
36  val l_soc = LazyModule(new XSTop())
37  val soc = Module(l_soc.module)
38  // Don't allow the top-level signals to be optimized out,
39  // so that we can re-use this SimTop for any generated Verilog RTL.
40  dontTouch(soc.io)
41
42  l_soc.module.dma <> 0.U.asTypeOf(l_soc.module.dma)
43
44  val l_simMMIO = LazyModule(new SimMMIO(l_soc.misc.peripheralNode.in.head._2))
45  val simMMIO = Module(l_simMMIO.module)
46  l_simMMIO.io_axi4 <> soc.peripheral
47
48  if(!useDRAMSim){
49    val l_simAXIMem = LazyModule(new AXI4RAMWrapper(
50      l_soc.misc.memAXI4SlaveNode, 8L * 1024 * 1024 * 1024, useBlackBox = true
51    ))
52    val simAXIMem = Module(l_simAXIMem.module)
53    l_simAXIMem.io_axi4 <> soc.memory
54  }
55
56  soc.io.clock := clock.asBool
57  soc.io.reset := reset.asBool
58  soc.io.extIntrs := simMMIO.io.interrupt.intrVec
59  soc.io.sram_config := 0.U
60  soc.io.pll0_lock := true.B
61  soc.io.cacheable_check := DontCare
62
63  val success = Wire(Bool())
64  val jtag = Module(new SimJTAG(tickDelay=3)(p)).connect(soc.io.systemjtag.jtag, clock, reset.asBool, ~reset.asBool, success)
65  soc.io.systemjtag.reset := reset
66  soc.io.systemjtag.mfr_id := 0.U(11.W)
67  soc.io.systemjtag.part_number := 0.U(16.W)
68  soc.io.systemjtag.version := 0.U(4.W)
69
70  val io = IO(new Bundle(){
71    val logCtrl = new LogCtrlIO
72    val perfInfo = new PerfInfoIO
73    val uart = new UARTIO
74    val memAXI = if(useDRAMSim) soc.memory.cloneType else null
75  })
76
77  simMMIO.io.uart <> io.uart
78
79  if(useDRAMSim){
80    io.memAXI <> soc.memory
81  }
82
83  if (!debugOpts.FPGAPlatform && (debugOpts.EnableDebug || debugOpts.EnablePerfDebug)) {
84    val timer = GTimer()
85    val logEnable = (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end)
86    ExcitingUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE")
87    ExcitingUtils.addSource(timer, "logTimestamp")
88  }
89
90  if (!debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug) {
91    val clean = io.perfInfo.clean
92    val dump = io.perfInfo.dump
93    ExcitingUtils.addSource(clean, "XSPERF_CLEAN")
94    ExcitingUtils.addSource(dump, "XSPERF_DUMP")
95  }
96
97  // Check and dispaly all source and sink connections
98  ExcitingUtils.fixConnections()
99  ExcitingUtils.checkAndDisplay()
100}
101
102object SimTop extends App {
103  override def main(args: Array[String]): Unit = {
104    // Keep this the same as TopMain except that SimTop is used here instead of XSTop
105    val (config, firrtlOpts) = ArgParser.parse(args)
106    XiangShanStage.execute(firrtlOpts, Seq(
107      ChiselGeneratorAnnotation(() => {
108        DisableMonitors(p => new SimTop()(p))(config)
109      })
110    ))
111    ElaborationArtefacts.files.foreach{ case (extension, contents) =>
112      writeOutputFile("./build", s"XSTop.${extension}", contents())
113    }
114  }
115}
116