1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import device.{AXI4MemorySlave, SimJTAG} 23import difftest._ 24import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule} 25import freechips.rocketchip.util.ElaborationArtefacts 26import utility.ChiselDB 27import top.TopMain.writeOutputFile 28import utility.GTimer 29import xiangshan.DebugOptionsKey 30import utility.Constantin 31 32class SimTop(implicit p: Parameters) extends Module { 33 val debugOpts = p(DebugOptionsKey) 34 35 val l_soc = LazyModule(new XSTop()) 36 val soc = Module(l_soc.module) 37 // Don't allow the top-level signals to be optimized out, 38 // so that we can re-use this SimTop for any generated Verilog RTL. 39 dontTouch(soc.io) 40 41 l_soc.module.dma <> 0.U.asTypeOf(l_soc.module.dma) 42 43 val l_simMMIO = LazyModule(new SimMMIO(l_soc.misc.peripheralNode.in.head._2)) 44 val simMMIO = Module(l_simMMIO.module) 45 l_simMMIO.io_axi4 <> soc.peripheral 46 47 val l_simAXIMem = AXI4MemorySlave( 48 l_soc.misc.memAXI4SlaveNode, 49 16L * 1024 * 1024 * 1024, 50 useBlackBox = true, 51 dynamicLatency = debugOpts.UseDRAMSim 52 ) 53 val simAXIMem = Module(l_simAXIMem.module) 54 l_simAXIMem.io_axi4 <> soc.memory 55 56 soc.io.clock := clock.asBool 57 soc.io.reset := reset.asAsyncReset 58 soc.io.extIntrs := simMMIO.io.interrupt.intrVec 59 soc.io.sram_config := 0.U 60 soc.io.pll0_lock := true.B 61 soc.io.cacheable_check := DontCare 62 soc.io.riscv_rst_vec.foreach(_ := 0x10000000L.U) 63 64 // soc.io.rtc_clock is a div100 of soc.io.clock 65 val rtcClockDiv = 100 66 val rtcTickCycle = rtcClockDiv / 2 67 val rtcCounter = RegInit(0.U(log2Ceil(rtcTickCycle + 1).W)) 68 rtcCounter := Mux(rtcCounter === (rtcTickCycle - 1).U, 0.U, rtcCounter + 1.U) 69 val rtcClock = RegInit(false.B) 70 when (rtcCounter === 0.U) { 71 rtcClock := ~rtcClock 72 } 73 soc.io.rtc_clock := rtcClock 74 75 val success = Wire(Bool()) 76 val jtag = Module(new SimJTAG(tickDelay=3)(p)).connect(soc.io.systemjtag.jtag, clock, reset.asBool, !reset.asBool, success) 77 soc.io.systemjtag.reset := reset.asAsyncReset 78 soc.io.systemjtag.mfr_id := 0.U(11.W) 79 soc.io.systemjtag.part_number := 0.U(16.W) 80 soc.io.systemjtag.version := 0.U(4.W) 81 82 val io = IO(new Bundle(){ 83 val logCtrl = new LogCtrlIO 84 val perfInfo = new PerfInfoIO 85 val uart = new UARTIO 86 }) 87 88 simMMIO.io.uart <> io.uart 89 90 if (!debugOpts.FPGAPlatform && (debugOpts.EnableDebug || debugOpts.EnablePerfDebug)) { 91 val timer = GTimer() 92 val logEnable = (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end) 93 ExcitingUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE") 94 ExcitingUtils.addSource(timer, "logTimestamp") 95 } 96 97 if (!debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug) { 98 val clean = io.perfInfo.clean 99 val dump = io.perfInfo.dump 100 ExcitingUtils.addSource(clean, "XSPERF_CLEAN") 101 ExcitingUtils.addSource(dump, "XSPERF_DUMP") 102 } 103 104 // Check and dispaly all source and sink connections 105 ExcitingUtils.fixConnections() 106 ExcitingUtils.checkAndDisplay() 107} 108 109object SimTop extends App { 110 override def main(args: Array[String]): Unit = { 111 // Keep this the same as TopMain except that SimTop is used here instead of XSTop 112 val (config, firrtlOpts, firrtlComplier) = ArgParser.parse(args) 113 Generator.execute( 114 firrtlOpts, 115 DisableMonitors(p => new SimTop()(p))(config), 116 firrtlComplier 117 ) 118 ChiselDB.addToElaborationArtefacts 119 Constantin.addToElaborationArtefacts 120 ElaborationArtefacts.files.foreach{ 121 case (extension, contents) => 122 val prefix = extension match { 123 case "h" | "cpp" => "chisel_db" 124 case "hxx" | "cxx" => "constantin" 125 case _ => "XSTop" 126 } 127 writeOutputFile("./build", s"$prefix.${extension}", contents()) 128 } 129 } 130} 131