1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chipsalliance.rocketchip.config.{Config, Parameters} 20import chisel3.stage.ChiselGeneratorAnnotation 21import chisel3._ 22import device.{AXI4RAMWrapper, SimJTAG} 23import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule, LazyModuleImp} 24import utils.GTimer 25import xiangshan.{DebugOptions, DebugOptionsKey} 26import chipsalliance.rocketchip.config._ 27import freechips.rocketchip.devices.debug._ 28import difftest._ 29 30class SimTop(implicit p: Parameters) extends Module { 31 val debugOpts = p(DebugOptionsKey) 32 val useDRAMSim = debugOpts.UseDRAMSim 33 34 val l_soc = LazyModule(new XSTop()) 35 val soc = Module(l_soc.module) 36 37 l_soc.module.dma <> DontCare 38 39 val l_simMMIO = LazyModule(new SimMMIO(l_soc.misc.peripheralNode.in.head._2)) 40 val simMMIO = Module(l_simMMIO.module) 41 l_simMMIO.io_axi4 <> soc.peripheral 42 43 if(!useDRAMSim){ 44 val l_simAXIMem = LazyModule(new AXI4RAMWrapper( 45 l_soc.misc.memAXI4SlaveNode, 8L * 1024 * 1024 * 1024, useBlackBox = true 46 )) 47 val simAXIMem = Module(l_simAXIMem.module) 48 l_simAXIMem.io_axi4 <> soc.memory 49 } 50 51 soc.io.clock := clock.asBool 52 soc.io.reset := reset.asBool 53 soc.io.extIntrs := simMMIO.io.interrupt.intrVec 54 soc.io.osc_clock := false.B 55 soc.io.sram_config := 0.U 56 soc.io.core_reset.foreach(_ := false.B) 57 58 val success = Wire(Bool()) 59 val jtag = Module(new SimJTAG(tickDelay=3)(p)).connect(soc.io.systemjtag.jtag, clock, reset.asBool, ~reset.asBool, success) 60 soc.io.systemjtag.reset := reset 61 soc.io.systemjtag.mfr_id := 0.U(11.W) 62 soc.io.systemjtag.part_number := 0.U(16.W) 63 soc.io.systemjtag.version := 0.U(4.W) 64 65 val io = IO(new Bundle(){ 66 val logCtrl = new LogCtrlIO 67 val perfInfo = new PerfInfoIO 68 val uart = new UARTIO 69 val memAXI = if(useDRAMSim) soc.memory.cloneType else null 70 }) 71 72 simMMIO.io.uart <> io.uart 73 74 if(useDRAMSim){ 75 io.memAXI <> soc.memory 76 } 77 78 if (debugOpts.EnableDebug || debugOpts.EnablePerfDebug) { 79 val timer = GTimer() 80 val logEnable = (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end) 81 ExcitingUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE") 82 ExcitingUtils.addSource(timer, "logTimestamp") 83 } 84 85 if (debugOpts.EnablePerfDebug) { 86 val clean = io.perfInfo.clean 87 val dump = io.perfInfo.dump 88 ExcitingUtils.addSource(clean, "XSPERF_CLEAN") 89 ExcitingUtils.addSource(dump, "XSPERF_DUMP") 90 } 91 92 // Check and dispaly all source and sink connections 93 ExcitingUtils.fixConnections() 94 ExcitingUtils.checkAndDisplay() 95} 96 97object SimTop extends App { 98 99 override def main(args: Array[String]): Unit = { 100 val (config, firrtlOpts) = ArgParser.parse(args, fpga = false) 101 // generate verilog 102 XiangShanStage.execute( 103 firrtlOpts, 104 Seq( 105 ChiselGeneratorAnnotation(() => DisableMonitors(p => new SimTop()(p))(config)) 106 ) 107 ) 108 } 109} 110