xref: /XiangShan/src/test/scala/top/SimTop.scala (revision c21bff99db38ffd5df19a9459a048e16b7b7cb23) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chipsalliance.rocketchip.config.{Config, Parameters}
20import chisel3.stage.ChiselGeneratorAnnotation
21import chisel3._
22import device.{AXI4RAMWrapper, SimJTAG}
23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
24import utils.GTimer
25import xiangshan.{DebugOptions, DebugOptionsKey}
26import chipsalliance.rocketchip.config._
27import freechips.rocketchip.devices.debug._
28import difftest._
29
30class SimTop(implicit p: Parameters) extends Module {
31  val debugOpts = p(DebugOptionsKey)
32  val useDRAMSim = debugOpts.UseDRAMSim
33
34  val l_soc = LazyModule(new XSTopWithoutDMA())
35  val soc = Module(l_soc.module)
36
37  val l_simMMIO = LazyModule(new SimMMIO(l_soc.peripheralNode.in.head._2))
38  val simMMIO = Module(l_simMMIO.module)
39  l_simMMIO.connectToSoC(l_soc)
40
41  if(!useDRAMSim){
42    val l_simAXIMem = LazyModule(new AXI4RAMWrapper(
43      l_soc.memAXI4SlaveNode, 8L * 1024 * 1024 * 1024, useBlackBox = true
44    ))
45    val simAXIMem = Module(l_simAXIMem.module)
46    l_simAXIMem.connectToSoC(l_soc)
47  }
48
49  soc.io.clock := clock.asBool()
50  soc.io.reset := reset.asBool()
51  soc.io.extIntrs := simMMIO.io.interrupt.intrVec
52
53  val success = Wire(Bool())
54  val jtag = Module(new SimJTAG(tickDelay=3)(p)).connect(soc.io.systemjtag.jtag, clock, reset.asBool, ~reset.asBool, success)
55  soc.io.systemjtag.reset := reset
56  soc.io.systemjtag.mfr_id := 0.U(11.W)
57  soc.io.systemjtag.part_number := 0.U(16.W)
58  soc.io.systemjtag.version := 0.U(4.W)
59
60  val io = IO(new Bundle(){
61    val logCtrl = new LogCtrlIO
62    val perfInfo = new PerfInfoIO
63    val uart = new UARTIO
64    val memAXI = if(useDRAMSim) l_soc.memory.cloneType else null
65  })
66
67  simMMIO.io.uart <> io.uart
68
69  if(useDRAMSim){
70    io.memAXI <> l_soc.memory
71  }
72
73  if (debugOpts.EnableDebug || debugOpts.EnablePerfDebug) {
74    val timer = GTimer()
75    val logEnable = (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end)
76    ExcitingUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE")
77    ExcitingUtils.addSource(timer, "logTimestamp")
78  }
79
80  if (debugOpts.EnablePerfDebug) {
81    val clean = io.perfInfo.clean
82    val dump = io.perfInfo.dump
83    ExcitingUtils.addSource(clean, "XSPERF_CLEAN")
84    ExcitingUtils.addSource(dump, "XSPERF_DUMP")
85  }
86
87  // Check and dispaly all source and sink connections
88  ExcitingUtils.fixConnections()
89  ExcitingUtils.checkAndDisplay()
90}
91
92object SimTop extends App {
93
94  override def main(args: Array[String]): Unit = {
95    val (config, firrtlOpts) = ArgParser.parse(args, fpga = false)
96    // generate verilog
97    XiangShanStage.execute(
98      firrtlOpts,
99      Seq(
100        ChiselGeneratorAnnotation(() => new SimTop()(config))
101      )
102    )
103  }
104}
105