1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import chisel3.stage.ChiselGeneratorAnnotation 23import device.{AXI4RAMWrapper, SimJTAG} 24import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule, LazyModuleImp} 25import utils.GTimer 26import xiangshan.{DebugOptions, DebugOptionsKey} 27import difftest._ 28import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule} 29import freechips.rocketchip.util.ElaborationArtefacts 30import huancun.utils.ChiselDB 31import top.TopMain.writeOutputFile 32import utils.GTimer 33import xiangshan.DebugOptionsKey 34 35class SimTop(implicit p: Parameters) extends Module { 36 val debugOpts = p(DebugOptionsKey) 37 val useDRAMSim = debugOpts.UseDRAMSim 38 39 val l_soc = LazyModule(new XSTop()) 40 val soc = Module(l_soc.module) 41 // Don't allow the top-level signals to be optimized out, 42 // so that we can re-use this SimTop for any generated Verilog RTL. 43 dontTouch(soc.io) 44 45 l_soc.module.dma <> 0.U.asTypeOf(l_soc.module.dma) 46 47 val l_simMMIO = LazyModule(new SimMMIO(l_soc.misc.peripheralNode.in.head._2)) 48 val simMMIO = Module(l_simMMIO.module) 49 l_simMMIO.io_axi4 <> soc.peripheral 50 51 if(!useDRAMSim){ 52 val l_simAXIMem = LazyModule(new AXI4RAMWrapper( 53 l_soc.misc.memAXI4SlaveNode, 8L * 1024 * 1024 * 1024, useBlackBox = true 54 )) 55 val simAXIMem = Module(l_simAXIMem.module) 56 l_simAXIMem.io_axi4 <> soc.memory 57 } 58 59 soc.io.clock := clock.asBool 60 soc.io.reset := reset.asBool 61 soc.io.extIntrs := simMMIO.io.interrupt.intrVec 62 soc.io.sram_config := 0.U 63 soc.io.pll0_lock := true.B 64 soc.io.cacheable_check := DontCare 65 soc.io.riscv_rst_vec.foreach(_ := 0x10000000L.U) 66 67 // soc.io.rtc_clock is a div100 of soc.io.clock 68 val rtcClockDiv = 100 69 val rtcTickCycle = rtcClockDiv / 2 70 val rtcCounter = RegInit(0.U(log2Ceil(rtcTickCycle + 1).W)) 71 rtcCounter := Mux(rtcCounter === (rtcTickCycle - 1).U, 0.U, rtcCounter + 1.U) 72 val rtcClock = RegInit(false.B) 73 when (rtcCounter === 0.U) { 74 rtcClock := ~rtcClock 75 } 76 soc.io.rtc_clock := rtcClock 77 78 val success = Wire(Bool()) 79 val jtag = Module(new SimJTAG(tickDelay=3)(p)).connect(soc.io.systemjtag.jtag, clock, reset.asBool, !reset.asBool, success) 80 soc.io.systemjtag.reset := reset 81 soc.io.systemjtag.mfr_id := 0.U(11.W) 82 soc.io.systemjtag.part_number := 0.U(16.W) 83 soc.io.systemjtag.version := 0.U(4.W) 84 85 val io = IO(new Bundle(){ 86 val logCtrl = new LogCtrlIO 87 val perfInfo = new PerfInfoIO 88 val uart = new UARTIO 89 val memAXI = if(useDRAMSim) soc.memory.cloneType else null 90 }) 91 92 simMMIO.io.uart <> io.uart 93 94 if(useDRAMSim){ 95 io.memAXI <> soc.memory 96 } 97 98 if (!debugOpts.FPGAPlatform && (debugOpts.EnableDebug || debugOpts.EnablePerfDebug)) { 99 val timer = GTimer() 100 val logEnable = (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end) 101 ExcitingUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE") 102 ExcitingUtils.addSource(timer, "logTimestamp") 103 } 104 105 if (!debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug) { 106 val clean = io.perfInfo.clean 107 val dump = io.perfInfo.dump 108 ExcitingUtils.addSource(clean, "XSPERF_CLEAN") 109 ExcitingUtils.addSource(dump, "XSPERF_DUMP") 110 } 111 112 // Check and dispaly all source and sink connections 113 ExcitingUtils.fixConnections() 114 ExcitingUtils.checkAndDisplay() 115} 116 117object SimTop extends App { 118 override def main(args: Array[String]): Unit = { 119 // Keep this the same as TopMain except that SimTop is used here instead of XSTop 120 val (config, firrtlOpts, firrtlComplier) = ArgParser.parse(args) 121 Generator.execute( 122 firrtlOpts, 123 DisableMonitors(p => new SimTop()(p))(config), 124 firrtlComplier 125 ) 126 ChiselDB.addToElaborationArtefacts 127 ElaborationArtefacts.files.foreach{ 128 case (extension, contents) => 129 val prefix = extension match { 130 case "h" | "cpp" => "chisel_db" 131 case _ => "XSTop" 132 } 133 writeOutputFile("./build", s"$prefix.${extension}", contents()) 134 } 135 } 136} 137