CSR: fix trap inst update condition

* Never update trap inst if TrapInstMod already has valid inst.
* CSR illegal has higher priority to update trap inst, since the inst executed in CSR is order tha

CSR: fix trap inst update condition

* Never update trap inst if TrapInstMod already has valid inst.
* CSR illegal has higher priority to update trap inst, since the inst executed in CSR is order than all insts in decode stage

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Backend: only store 16 bits instr in tval when C extension EX_II occurs

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded in

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded instruciton to IBuffer if the C extension 16 bits instruction is illegal.
* No need to use bypass illBuf, since the origin 16 bits instruction will be passed in the ctrlflow bundle.
* IBuffer
* Merge exceptionType and crossPageIPFFix into 3bit field, which type is IBufferExceptionType.
* IBufferExceptionType can hold illegal instruction exception.
* Backend
* CSROpType.ro is removed, since we can use rs1 and rd passed in imm field to distinguish CSRR and CSRW in CSR module.
* Create TrapInstMod to store the trap instruction and handle its update.

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Backend: fix s/shvstvala, updata xtvala when EX_VI

Backend: support Shvstvala and Sstvala extension

zfhmin:add zfhmin extensions

*decode unit adds decoding of zfhmin extension related instructions
*Re exemplified the functional units for scalar fpcvt

FPU: add FP16 in FType

* Update box and unbox functions
* Todo: use fmt field encoding in riscv FP instructions instead of customized encoding.

PMA, MMU: Fix bug of PA48 (#3424)

*PMA: Extend the default memory space from 0x1000000000L to
0x1000000000000L
*MMU: only trigger accessfault when ppn above
PADDRBITS(48)-OFFSETBITS(12) is not ze

PMA, MMU: Fix bug of PA48 (#3424)

*PMA: Extend the default memory space from 0x1000000000L to
0x1000000000000L
*MMU: only trigger accessfault when ppn above
PADDRBITS(48)-OFFSETBITS(12) is not zero

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DebugModule: fix bug, trap don't take place in dmode. (#3422)

Traps don’t take place in Debug Mode. Instead, they end execution of the
program buffer and the hart remains in Debug Mode. Because the

DebugModule: fix bug, trap don't take place in dmode. (#3422)

Traps don’t take place in Debug Mode. Instead, they end execution of the
program buffer and the hart remains in Debug Mode. Because they do not
trap to M-mode, they do not update registers such as , `mepc`, `mcause`,
`mtval`, `mtval2`, and `mtinst`. The same is true for the equivalent
privileged registers that are updated when trapping to other modes.

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MMU, RVH: add the check of gpaddr high bits and fix some bugs (#3348)

Trigger: refactor trigger information in pipeline. (#3403)

RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

--

RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

---------

Co-authored-by: xiaofeibao <[email protected]>

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RVA23: Support Sv48 & Sv48x4 (#3406)

Co-authored-by: Xuan Hu <[email protected]>

fix the wrong condition of Mux1H about tval2 that makes wrong gpa written into htval or mtval2

sireg: fix the condition of rwSireg_EX_VI. (#3394)

According AIA spec, when vsiselect has the number of an inaccessible
register, attempts from VS-mode to access sireg
(really vsireg) raise a virt

sireg: fix the condition of rwSireg_EX_VI. (#3394)

According AIA spec, when vsiselect has the number of an inaccessible
register, attempts from VS-mode to access sireg
(really vsireg) raise a virtual instruction exception.
But 0x070-0x0ff are external interrupts (IMSIC only), or inaccessible.
And we has implemented IMSIC.

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Vfalu: fix fflagsRedMask use outVecCtrl (#3399)

CSR: miselect, siselect, vsiselect should have reset value since they are WARL

ROB: fix the bug that the interrupt_safe of CSR instruction is 1

csr: execute inst will raise EX_II when rm is reserved value.

* When 0 <= inst.rm <= 4, execute inst as usual.
* When inst.rm = 5/6, execute inst will raise EX_II.
* When inst.rm = 7, rm

csr: execute inst will raise EX_II when rm is reserved value.

* When 0 <= inst.rm <= 4, execute inst as usual.
* When inst.rm = 5/6, execute inst will raise EX_II.
* When inst.rm = 7, rm = frm.data. if frm.data > 4 will raise EX_II.

* Meanwhile, flush pipe when
* 1. wen frm CSR and wdata > 4
* 2. wen fcsr CSR and wdata(7, 5) > 4
* 3. wen frm/fcsr CSR and frm.rdata is reserved

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CSR, RVH: fix the wrong val writen in htval when having igpf

CSR: fix custom IRQ injection mechanism

* The injected interrupts for HS mode can set some bits in mIRVec and hsIRVec.
* `mIRVec` holds the highest priority interrupt numbered from 1 to 63. Only int

CSR: fix custom IRQ injection mechanism

* The injected interrupts for HS mode can set some bits in mIRVec and hsIRVec.
* `mIRVec` holds the highest priority interrupt numbered from 1 to 63. Only interrupt 1~13 can trap in M mode. And interrupt 14~63 must trap in HS mode or VS mode, since bits in mideleg(63,14) are read-only 0.
* `hsIRVec` holds the mip parts(by mIRVec & mideleg) and mvip parts(by mIRVec & ~mideleg & mvien) interrupts.
* `vsIRVec` holds the sip|hip parts(by hsIRVec & hideleg) and hvip parts(by hsIRVec & ~hideleg & hvien) interrupts.

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VFALU and VFMA: fix bug of vlmul when outWiden is 1 (#3352)

CSR: initialize vstart to avoid X propagation at DecodeStage

CSR: use "ignore illegal write" WARL strategy for tselect (#3353)

CSR: add custom IRQ injection mechanism (#3338)

* All major interrupts have been splited into 7 groups
* Custom highest group
* Local high group
* Custom middle-high group
* Priviledge a

CSR: add custom IRQ injection mechanism (#3338)

* All major interrupts have been splited into 7 groups
* Custom highest group
* Local high group
* Custom middle-high group
* Priviledge architecture group
* Custom middle-low group
* Local low group
* Custom lowest group

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