1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.backend.Bundles.TrapInstInfo 14import xiangshan.backend.decode.Imm_Z 15import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 16import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 17import xiangshan.frontend.FtqPtr 18 19class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 20 with HasCircularQueuePtrHelper 21{ 22 val csrIn = io.csrio.get 23 val csrOut = io.csrio.get 24 val csrToDecode = io.csrToDecode.get 25 26 val setFsDirty = csrIn.fpu.dirty_fs 27 val setFflags = csrIn.fpu.fflags 28 29 val setVsDirty = csrIn.vpu.dirty_vs 30 val setVstart = csrIn.vpu.set_vstart 31 val setVtype = csrIn.vpu.set_vtype 32 val setVxsat = csrIn.vpu.set_vxsat 33 val vlFromPreg = csrIn.vpu.vl 34 35 val flushPipe = Wire(Bool()) 36 val flush = io.flush.valid 37 38 val (valid, src1, imm, func) = ( 39 io.in.valid, 40 io.in.bits.data.src(0), 41 io.in.bits.data.imm(Imm_Z().len - 1, 0), 42 io.in.bits.ctrl.fuOpType 43 ) 44 45 // split imm/src1/rd from IMM_Z: src1/rd for tval 46 val addr = Imm_Z().getCSRAddr(imm) 47 val rd = Imm_Z().getRD(imm) 48 val rs1 = Imm_Z().getRS1(imm) 49 val imm5 = Imm_Z().getImm5(imm) 50 val csri = ZeroExt(imm5, XLEN) 51 52 import CSRConst._ 53 54 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 55 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 56 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 57 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 58 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 59 private val isWfi = CSROpType.isWfi(func) 60 private val isCSRAcc = CSROpType.isCsrAccess(func) 61 62 val csrMod = Module(new NewCSR) 63 val trapInstMod = Module(new TrapInstMod) 64 65 private val privState = csrMod.io.status.privState 66 // The real reg value in CSR, with no read mask 67 private val regOut = csrMod.io.out.bits.regOut 68 private val src = Mux(CSROpType.needImm(func), csri, src1) 69 private val wdata = LookupTree(func, Seq( 70 CSROpType.wrt -> src1, 71 CSROpType.set -> (regOut | src1), 72 CSROpType.clr -> (regOut & (~src1).asUInt), 73 CSROpType.wrti -> csri, 74 CSROpType.seti -> (regOut | csri), 75 CSROpType.clri -> (regOut & (~csri).asUInt), 76 )) 77 78 private val csrAccess = valid && CSROpType.isCsrAccess(func) 79 private val csrWen = valid && ( 80 CSROpType.isCSRRW(func) || 81 CSROpType.isCSRRSorRC(func) && rs1 =/= 0.U 82 ) 83 private val csrRen = valid && ( 84 CSROpType.isCSRRW(func) && rd =/= 0.U || 85 CSROpType.isCSRRSorRC(func) 86 ) 87 88 csrMod.io.in match { 89 case in => 90 in.valid := valid 91 in.bits.wen := csrWen 92 in.bits.ren := csrRen 93 in.bits.op := CSROpType.getCSROp(func) 94 in.bits.addr := addr 95 in.bits.src := src 96 in.bits.wdata := wdata 97 in.bits.mret := isMret 98 in.bits.sret := isSret 99 in.bits.dret := isDret 100 } 101 csrMod.io.trapInst := trapInstMod.io.currentTrapInst 102 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 103 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 104 105 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 106 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 107 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 108 csrMod.io.fromRob.trap.bits.pcGPA := csrIn.exception.bits.gpaddr 109 // Todo: shrink the width of trap vector. 110 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 111 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 112 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 113 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 114 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 115 csrMod.io.fromRob.trap.bits.trigger := csrIn.exception.bits.trigger 116 csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls 117 118 csrMod.io.fromRob.commit.fflags := setFflags 119 csrMod.io.fromRob.commit.fsDirty := setFsDirty 120 csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid 121 csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits 122 csrMod.io.fromRob.commit.vsDirty := setVsDirty 123 csrMod.io.fromRob.commit.vstart := setVstart 124 csrMod.io.fromRob.commit.vl := vlFromPreg 125 // Todo: correct vtype 126 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 127 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 128 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 129 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 130 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 131 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 132 133 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 134 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 135 136 csrMod.io.perf := csrIn.perf 137 138 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 139 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 140 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 141 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 142 csrMod.platformIRP.STIP := false.B 143 csrMod.platformIRP.VSEIP := false.B // Todo 144 csrMod.platformIRP.VSTIP := false.B // Todo 145 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 146 147 csrMod.io.fromTop.hartId := io.csrin.get.hartId 148 csrMod.io.fromTop.clintTime := io.csrin.get.clintTime 149 private val csrModOutValid = csrMod.io.out.valid 150 private val csrModOut = csrMod.io.out.bits 151 152 trapInstMod.io.fromDecode.trapInstInfo := io.csrin.get.trapInstInfo 153 trapInstMod.io.fromRob.flush.valid := io.flush.valid 154 trapInstMod.io.fromRob.flush.bits.ftqPtr := io.flush.bits.ftqIdx 155 trapInstMod.io.fromRob.flush.bits.ftqOffset := io.flush.bits.ftqOffset 156 trapInstMod.io.faultCsrUop.valid := csrMod.io.out.valid && (csrMod.io.out.bits.EX_II || csrMod.io.out.bits.EX_VI) 157 trapInstMod.io.faultCsrUop.bits.fuOpType := DataHoldBypass(io.in.bits.ctrl.fuOpType, io.in.fire) 158 trapInstMod.io.faultCsrUop.bits.imm := DataHoldBypass(io.in.bits.data.imm, io.in.fire) 159 // Clear trap instruction when any trap occurs. 160 trapInstMod.io.readClear := csrMod.io.fromRob.trap.valid 161 162 private val imsic = Module(new IMSIC(NumVSIRFiles = 5, NumHart = 1, XLEN = 64, NumIRSrc = 256)) 163 imsic.i.hartId := io.csrin.get.hartId 164 imsic.i.msiInfo := io.csrin.get.msiInfo 165 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 166 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 167 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 168 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 169 imsic.i.csr.vgein := csrMod.toAIA.vgein 170 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 171 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 172 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 173 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 174 imsic.i.csr.wdata.bits.op := csrMod.toAIA.wdata.bits.op 175 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 176 177 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 178 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 179 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 180 csrMod.fromAIA.meip := imsic.o.meip 181 csrMod.fromAIA.seip := imsic.o.seip 182 csrMod.fromAIA.vseip := imsic.o.vseip 183 csrMod.fromAIA.mtopei := imsic.o.mtopei 184 csrMod.fromAIA.stopei := imsic.o.stopei 185 csrMod.fromAIA.vstopei := imsic.o.vstopei 186 187 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 188 import ExceptionNO._ 189 exceptionVec(EX_BP ) := isEbreak 190 exceptionVec(EX_MCALL ) := isEcall && privState.isModeM 191 exceptionVec(EX_HSCALL) := isEcall && privState.isModeHS 192 exceptionVec(EX_VSCALL) := isEcall && privState.isModeVS 193 exceptionVec(EX_UCALL ) := isEcall && privState.isModeHUorVU 194 exceptionVec(EX_II ) := csrMod.io.out.bits.EX_II 195 exceptionVec(EX_VI ) := csrMod.io.out.bits.EX_VI 196 197 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 198 199 // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN 200 val isXRetFlag = RegInit(false.B) 201 isXRetFlag := Mux1H(Seq( 202 DelayN(flush, 5) -> false.B, 203 isXRet -> true.B, 204 )) 205 206 flushPipe := csrMod.io.out.bits.flushPipe 207 208 // tlb 209 val tlb = Wire(new TlbCsrBundle) 210 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 211 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 212 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 213 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 214 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 215 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 216 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 217 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 218 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 219 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 220 tlb.hgatp.vmid := csrMod.io.tlb.hgatp.VMID.asUInt 221 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 222 223 // expose several csr bits for tlb 224 tlb.priv.mxr := csrMod.io.tlb.mxr 225 tlb.priv.sum := csrMod.io.tlb.sum 226 tlb.priv.vmxr := csrMod.io.tlb.vmxr 227 tlb.priv.vsum := csrMod.io.tlb.vsum 228 tlb.priv.spvp := csrMod.io.tlb.spvp 229 tlb.priv.virt := csrMod.io.tlb.dvirt 230 tlb.priv.imode := csrMod.io.tlb.imode 231 tlb.priv.dmode := csrMod.io.tlb.dmode 232 233 io.in.ready := true.B // Todo: Async read imsic may block CSR 234 io.out.valid := csrModOutValid 235 io.out.bits.ctrl.exceptionVec.get := exceptionVec 236 io.out.bits.ctrl.flushPipe.get := flushPipe 237 io.out.bits.res.data := csrMod.io.out.bits.rData 238 239 io.out.bits.res.redirect.get.valid := isXRet 240 val redirect = io.out.bits.res.redirect.get.bits 241 redirect := 0.U.asTypeOf(redirect) 242 redirect.level := RedirectLevel.flushAfter 243 redirect.robIdx := io.in.bits.ctrl.robIdx 244 redirect.ftqIdx := io.in.bits.ctrl.ftqIdx.get 245 redirect.ftqOffset := io.in.bits.ctrl.ftqOffset.get 246 redirect.cfiUpdate.predTaken := true.B 247 redirect.cfiUpdate.taken := true.B 248 redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc 249 // Only mispred will send redirect to frontend 250 redirect.cfiUpdate.isMisPred := true.B 251 252 connect0LatencyCtrlSingal 253 254 // Todo: summerize all difftest skip condition 255 csrOut.isPerfCnt := csrMod.io.out.bits.isPerfCnt && csrModOutValid && func =/= CSROpType.jmp 256 csrOut.fpu.frm := csrMod.io.status.fpState.frm.asUInt 257 csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt 258 csrOut.vpu.vxrm := csrMod.io.status.vecState.vxrm.asUInt 259 260 csrOut.isXRet := isXRetFlag 261 262 csrOut.trapTarget := csrMod.io.out.bits.targetPc 263 csrOut.interrupt := csrMod.io.status.interrupt 264 csrOut.wfi_event := csrMod.io.status.wfiEvent 265 266 csrOut.tlb := tlb 267 268 csrOut.debugMode := csrMod.io.status.debugMode 269 270 csrOut.customCtrl match { 271 case custom => 272 custom.l1I_pf_enable := csrMod.io.status.custom.l1I_pf_enable 273 custom.l2_pf_enable := csrMod.io.status.custom.l2_pf_enable 274 custom.l1D_pf_enable := csrMod.io.status.custom.l1D_pf_enable 275 custom.l1D_pf_train_on_hit := csrMod.io.status.custom.l1D_pf_train_on_hit 276 custom.l1D_pf_enable_agt := csrMod.io.status.custom.l1D_pf_enable_agt 277 custom.l1D_pf_enable_pht := csrMod.io.status.custom.l1D_pf_enable_pht 278 custom.l1D_pf_active_threshold := csrMod.io.status.custom.l1D_pf_active_threshold 279 custom.l1D_pf_active_stride := csrMod.io.status.custom.l1D_pf_active_stride 280 custom.l1D_pf_enable_stride := csrMod.io.status.custom.l1D_pf_enable_stride 281 custom.l2_pf_store_only := csrMod.io.status.custom.l2_pf_store_only 282 // ICache 283 custom.icache_parity_enable := csrMod.io.status.custom.icache_parity_enable 284 // Load violation predictor 285 custom.lvpred_disable := csrMod.io.status.custom.lvpred_disable 286 custom.no_spec_load := csrMod.io.status.custom.no_spec_load 287 custom.storeset_wait_store := csrMod.io.status.custom.storeset_wait_store 288 custom.storeset_no_fast_wakeup := csrMod.io.status.custom.storeset_no_fast_wakeup 289 custom.lvpred_timeout := csrMod.io.status.custom.lvpred_timeout 290 // Branch predictor 291 custom.bp_ctrl := csrMod.io.status.custom.bp_ctrl 292 // Memory Block 293 custom.sbuffer_threshold := csrMod.io.status.custom.sbuffer_threshold 294 custom.ldld_vio_check_enable := csrMod.io.status.custom.ldld_vio_check_enable 295 custom.soft_prefetch_enable := csrMod.io.status.custom.soft_prefetch_enable 296 custom.cache_error_enable := csrMod.io.status.custom.cache_error_enable 297 custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable 298 custom.hd_misalign_st_enable := csrMod.io.status.custom.hd_misalign_st_enable 299 custom.hd_misalign_ld_enable := csrMod.io.status.custom.hd_misalign_ld_enable 300 // Rename 301 custom.fusion_enable := csrMod.io.status.custom.fusion_enable 302 custom.wfi_enable := csrMod.io.status.custom.wfi_enable 303 // distribute csr write signal 304 // write to frontend and memory 305 custom.distribute_csr.w.valid := csrWen 306 custom.distribute_csr.w.bits.addr := addr 307 custom.distribute_csr.w.bits.data := wdata 308 // rename single step 309 custom.singlestep := csrMod.io.status.singleStepFlag 310 // trigger 311 custom.frontend_trigger := csrMod.io.status.frontendTrigger 312 custom.mem_trigger := csrMod.io.status.memTrigger 313 // virtual mode 314 custom.virtMode := csrMod.io.status.privState.V.asBool 315 } 316 317 csrToDecode := csrMod.io.toDecode 318} 319 320class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 321 val hartId = Input(UInt(8.W)) 322 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 323 val clintTime = Input(ValidIO(UInt(64.W))) 324 val trapInstInfo = Input(ValidIO(new TrapInstInfo)) 325} 326 327class CSRToDecode(implicit p: Parameters) extends XSBundle { 328 val illegalInst = new Bundle { 329 /** 330 * illegal sfence.vma, sinval.vma 331 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 332 */ 333 val sfenceVMA = Bool() 334 335 /** 336 * illegal sfence.w.inval sfence.inval.ir 337 * raise EX_II when isModeHU 338 */ 339 val sfencePart = Bool() 340 341 /** 342 * illegal hfence.gvma, hinval.gvma 343 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 344 * the condition is the same as sfenceVMA 345 */ 346 val hfenceGVMA = Bool() 347 348 /** 349 * illegal hfence.vvma, hinval.vvma 350 * raise EX_II when isModeHU 351 */ 352 val hfenceVVMA = Bool() 353 354 /** 355 * illegal hlv, hlvx, and hsv 356 * raise EX_II when isModeHU && hstatus.HU=0 357 */ 358 val hlsv = Bool() 359 360 /** 361 * decode all fp inst or all vecfp inst 362 * raise EX_II when FS=Off 363 */ 364 val fsIsOff = Bool() 365 366 /** 367 * decode all vec inst 368 * raise EX_II when VS=Off 369 */ 370 val vsIsOff = Bool() 371 372 /** 373 * illegal wfi 374 * raise EX_II when isModeHU || !isModeM && mstatus.TW=1 375 */ 376 val wfi = Bool() 377 378 /** 379 * frm reserved 380 * raise EX_II when frm.data > 4 381 */ 382 val frm = Bool() 383 } 384 val virtualInst = new Bundle { 385 /** 386 * illegal sfence.vma, svinval.vma 387 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 388 */ 389 val sfenceVMA = Bool() 390 391 /** 392 * illegal sfence.w.inval sfence.inval.ir 393 * raise EX_VI when isModeVU 394 */ 395 val sfencePart = Bool() 396 397 /** 398 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 399 * raise EX_VI when isModeVS || isModeVU 400 */ 401 val hfence = Bool() 402 403 /** 404 * illegal hlv, hlvx, and hsv 405 * raise EX_VI when isModeVS || isModeVU 406 */ 407 val hlsv = Bool() 408 409 /** 410 * illegal wfi 411 * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1 412 */ 413 val wfi = Bool() 414 } 415}