xref: /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapInstMod.scala (revision eec4ee3a396d14adf3da7decb9a432feae8c62e0) 
1package xiangshan.backend.fu.NewCSR
2
3import chisel3._
4import chisel3.util._
5import org.chipsalliance.cde.config.Parameters
6import utility.{HasCircularQueuePtrHelper, XSError}
7import xiangshan._
8import xiangshan.backend.Bundles.TrapInstInfo
9import xiangshan.backend.decode.Imm_Z
10import xiangshan.frontend.FtqPtr
11import xiangshan.backend.decode.isa.bitfield.OPCODE5Bit
12
13class FtqInfo(implicit p: Parameters) extends XSBundle {
14  val ftqPtr = new FtqPtr()
15  val ftqOffset = UInt(log2Up(PredictWidth).W)
16}
17
18class TrapInstMod(implicit p: Parameters) extends Module with HasCircularQueuePtrHelper {
19  val io = IO(new Bundle {
20    val fromDecode = Input(new Bundle {
21      val trapInstInfo = ValidIO(new TrapInstInfo)
22    })
23
24    val fromRob = Input(new Bundle {
25      val flush = ValidIO(new FtqInfo)
26    })
27
28    val faultCsrUop = Input(ValidIO(new Bundle {
29      val fuOpType = FuOpType()
30      val imm      = UInt(Imm_Z().len.W)
31    }))
32
33    val readClear = Input(Bool())
34    val currentTrapInst = Output(ValidIO(UInt(32.W)))
35  })
36
37  // alias
38  val flush = io.fromRob.flush
39  val newTrapInstInfo = io.fromDecode.trapInstInfo
40
41  val valid = RegInit(false.B)
42  val trapInstInfo = Reg(new TrapInstInfo)
43
44  val csrAddr = Imm_Z().getCSRAddr(io.faultCsrUop.bits.imm)
45  val rs1 = Imm_Z().getRS1(io.faultCsrUop.bits.imm)
46  val rd = Imm_Z().getRD(io.faultCsrUop.bits.imm)
47  val func3 = CSROpType.getFunc3(io.faultCsrUop.bits.fuOpType)
48
49  val csrInst = Cat(csrAddr, rs1, func3, rd, OPCODE5Bit.SYSTEM, "b11".U)
50  require(csrInst.getWidth == 32)
51
52  val newCSRInstValid = io.faultCsrUop.valid
53  val newCSRInst = WireInit(0.U.asTypeOf(new TrapInstInfo))
54  newCSRInst.instr := csrInst
55
56  when (flush.valid && valid && trapInstInfo.needFlush(flush.bits.ftqPtr, flush.bits.ftqOffset)) {
57    valid := false.B
58  }.elsewhen(io.readClear) {
59    valid := false.B
60  }.elsewhen(newCSRInstValid) {
61    valid := true.B
62    trapInstInfo := newCSRInst
63  }.elsewhen(newTrapInstInfo.valid && !valid) {
64    valid := true.B
65    trapInstInfo := newTrapInstInfo.bits
66    trapInstInfo.instr := Mux(
67      newTrapInstInfo.bits.instr(1, 0) === "b11".U,
68      newTrapInstInfo.bits.instr,
69      newTrapInstInfo.bits.instr(15, 0)
70    )
71  }
72
73  io.currentTrapInst.valid := valid
74  io.currentTrapInst.bits := trapInstInfo.instr
75}
76