1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.backend.Bundles.TrapInst 14import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 15import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 16import xiangshan.frontend.FtqPtr 17 18class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 19 with HasCircularQueuePtrHelper 20{ 21 val csrIn = io.csrio.get 22 val csrOut = io.csrio.get 23 val csrToDecode = io.csrToDecode.get 24 25 val setFsDirty = csrIn.fpu.dirty_fs 26 val setFflags = csrIn.fpu.fflags 27 28 val setVsDirty = csrIn.vpu.dirty_vs 29 val setVstart = csrIn.vpu.set_vstart 30 val setVtype = csrIn.vpu.set_vtype 31 val setVxsat = csrIn.vpu.set_vxsat 32 val vlFromPreg = csrIn.vpu.vl 33 34 val flushPipe = Wire(Bool()) 35 val flush = io.flush.valid 36 37 val (valid, src1, src2, func) = ( 38 io.in.valid, 39 io.in.bits.data.src(0), 40 io.in.bits.data.imm, 41 io.in.bits.ctrl.fuOpType 42 ) 43 44 // split imm/src1/rd from IMM_Z: src1/rd for tval 45 val rd = src2(21, 17) 46 val addr = src2(11, 0) 47 val rs1 = src2(16, 12) 48 val csri = ZeroExt(src2(16, 12), XLEN) 49 50 import CSRConst._ 51 52 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 53 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 54 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 55 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 56 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 57 private val isWfi = CSROpType.isWfi(func) 58 private val isCSRAcc = CSROpType.isCsrAccess(func) 59 60 val csrMod = Module(new NewCSR) 61 62 private val privState = csrMod.io.status.privState 63 // The real reg value in CSR, with no read mask 64 private val regOut = csrMod.io.out.bits.regOut 65 private val src = Mux(CSROpType.needImm(func), csri, src1) 66 private val wdata = LookupTree(func, Seq( 67 CSROpType.wrt -> src1, 68 CSROpType.set -> (regOut | src1), 69 CSROpType.clr -> (regOut & (~src1).asUInt), 70 CSROpType.wrti -> csri, 71 CSROpType.seti -> (regOut | csri), 72 CSROpType.clri -> (regOut & (~csri).asUInt), 73 )) 74 75 private val csrAccess = valid && CSROpType.isCsrAccess(func) 76 private val csrWen = valid && CSROpType.notReadOnly(func) 77 //trap inst 78 private val hasWrittenReg = RegInit(false.B) 79 private val isCSRIllegalInst = csrMod.io.out.bits.EX_II 80 // restore CSR inst 81 private val func3 = LookupTree(func, Seq( 82 CSROpType.wrt -> "b001".U, 83 CSROpType.set -> "b010".U, 84 CSROpType.clr -> "b011".U, 85 CSROpType.wrti -> "b101".U, 86 CSROpType.seti -> "b110".U, 87 CSROpType.clri -> "b111".U, 88 CSROpType.roset -> "b010".U, 89 CSROpType.roclr -> "b011".U, 90 )) 91 val CSRTrapInstr = Cat(addr, rs1, func3, rd, "b1110011".U) 92 val CSRTrapInst = Wire(new TrapInst) 93 CSRTrapInst.instr := CSRTrapInstr 94 CSRTrapInst.ftqIdx := io.in.bits.ctrl.ftqIdx.get 95 CSRTrapInst.ftqOffset := io.in.bits.ctrl.ftqOffset.get 96 97 // csr EXII is always older then decode EXII 98 val trapInstWen = isCSRIllegalInst || (csrIn.trapInst.valid && !hasWrittenReg) 99 val trapInstWdata = Mux(isCSRIllegalInst, CSRTrapInst, csrIn.trapInst.bits) 100 when(trapInstWen && !hasWrittenReg) { 101 hasWrittenReg := true.B 102 } 103 val trapInstReg = RegEnable(trapInstWdata, 0.U.asTypeOf(new TrapInst), trapInstWen) 104 val trapInstRen = csrMod.io.out.bits.trapInstRen 105 val trapInstRdata = WireInit(0.U(32.W)) 106 val needFlush = trapInstReg.needFlush(io.flush.bits.ftqIdx, io.flush.bits.ftqOffset) && io.flush.valid 107 dontTouch(needFlush) 108 when(trapInstRen && hasWrittenReg ) { 109 trapInstRdata := trapInstReg.instr 110 hasWrittenReg := false.B 111 } 112 when(needFlush) { 113 trapInstReg := 0.U.asTypeOf(new TrapInst) 114 hasWrittenReg := false.B 115 } 116 117 csrMod.io.in match { 118 case in => 119 in.valid := valid 120 in.bits.wen := csrWen 121 in.bits.ren := csrAccess 122 in.bits.op := CSROpType.getCSROp(func) 123 in.bits.addr := addr 124 in.bits.src := src 125 in.bits.wdata := wdata 126 in.bits.mret := isMret 127 in.bits.sret := isSret 128 in.bits.dret := isDret 129 } 130 csrMod.io.trapInstRdata := trapInstRdata 131 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 132 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 133 134 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 135 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 136 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 137 csrMod.io.fromRob.trap.bits.pcGPA := csrIn.exception.bits.gpaddr 138 // Todo: shrink the width of trap vector. 139 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 140 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 141 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 142 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 143 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 144 csrMod.io.fromRob.trap.bits.trigger := csrIn.exception.bits.trigger 145 csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls 146 147 csrMod.io.fromRob.commit.fflags := setFflags 148 csrMod.io.fromRob.commit.fsDirty := setFsDirty 149 csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid 150 csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits 151 csrMod.io.fromRob.commit.vsDirty := setVsDirty 152 csrMod.io.fromRob.commit.vstart := setVstart 153 csrMod.io.fromRob.commit.vl := vlFromPreg 154 // Todo: correct vtype 155 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 156 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 157 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 158 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 159 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 160 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 161 162 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 163 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 164 165 csrMod.io.perf := csrIn.perf 166 167 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 168 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 169 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 170 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 171 csrMod.platformIRP.STIP := false.B 172 csrMod.platformIRP.VSEIP := false.B // Todo 173 csrMod.platformIRP.VSTIP := false.B // Todo 174 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 175 176 csrMod.io.fromTop.hartId := io.csrin.get.hartId 177 csrMod.io.fromTop.clintTime := io.csrin.get.clintTime 178 private val csrModOutValid = csrMod.io.out.valid 179 private val csrModOut = csrMod.io.out.bits 180 181 private val imsic = Module(new IMSIC(NumVSIRFiles = 5, NumHart = 1, XLEN = 64, NumIRSrc = 256)) 182 imsic.i.hartId := io.csrin.get.hartId 183 imsic.i.msiInfo := io.csrin.get.msiInfo 184 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 185 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 186 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 187 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 188 imsic.i.csr.vgein := csrMod.toAIA.vgein 189 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 190 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 191 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 192 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 193 imsic.i.csr.wdata.bits.op := csrMod.toAIA.wdata.bits.op 194 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 195 196 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 197 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 198 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 199 csrMod.fromAIA.meip := imsic.o.meip 200 csrMod.fromAIA.seip := imsic.o.seip 201 csrMod.fromAIA.vseip := imsic.o.vseip 202 csrMod.fromAIA.mtopei := imsic.o.mtopei 203 csrMod.fromAIA.stopei := imsic.o.stopei 204 csrMod.fromAIA.vstopei := imsic.o.vstopei 205 206 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 207 import ExceptionNO._ 208 exceptionVec(EX_BP ) := isEbreak 209 exceptionVec(EX_MCALL ) := isEcall && privState.isModeM 210 exceptionVec(EX_HSCALL) := isEcall && privState.isModeHS 211 exceptionVec(EX_VSCALL) := isEcall && privState.isModeVS 212 exceptionVec(EX_UCALL ) := isEcall && privState.isModeHUorVU 213 exceptionVec(EX_II ) := csrMod.io.out.bits.EX_II 214 exceptionVec(EX_VI ) := csrMod.io.out.bits.EX_VI 215 216 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 217 218 // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN 219 val isXRetFlag = RegInit(false.B) 220 isXRetFlag := Mux1H(Seq( 221 DelayN(flush, 5) -> false.B, 222 isXRet -> true.B, 223 )) 224 225 flushPipe := csrMod.io.out.bits.flushPipe 226 227 // tlb 228 val tlb = Wire(new TlbCsrBundle) 229 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 230 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 231 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 232 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 233 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 234 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 235 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 236 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 237 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 238 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 239 tlb.hgatp.vmid := csrMod.io.tlb.hgatp.VMID.asUInt 240 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 241 242 // expose several csr bits for tlb 243 tlb.priv.mxr := csrMod.io.tlb.mxr 244 tlb.priv.sum := csrMod.io.tlb.sum 245 tlb.priv.vmxr := csrMod.io.tlb.vmxr 246 tlb.priv.vsum := csrMod.io.tlb.vsum 247 tlb.priv.spvp := csrMod.io.tlb.spvp 248 tlb.priv.virt := csrMod.io.tlb.dvirt 249 tlb.priv.imode := csrMod.io.tlb.imode 250 tlb.priv.dmode := csrMod.io.tlb.dmode 251 252 io.in.ready := true.B // Todo: Async read imsic may block CSR 253 io.out.valid := csrModOutValid 254 io.out.bits.ctrl.exceptionVec.get := exceptionVec 255 io.out.bits.ctrl.flushPipe.get := flushPipe 256 io.out.bits.res.data := csrMod.io.out.bits.rData 257 258 io.out.bits.res.redirect.get.valid := isXRet 259 val redirect = io.out.bits.res.redirect.get.bits 260 redirect := 0.U.asTypeOf(redirect) 261 redirect.level := RedirectLevel.flushAfter 262 redirect.robIdx := io.in.bits.ctrl.robIdx 263 redirect.ftqIdx := io.in.bits.ctrl.ftqIdx.get 264 redirect.ftqOffset := io.in.bits.ctrl.ftqOffset.get 265 redirect.cfiUpdate.predTaken := true.B 266 redirect.cfiUpdate.taken := true.B 267 redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc 268 // Only mispred will send redirect to frontend 269 redirect.cfiUpdate.isMisPred := true.B 270 271 connect0LatencyCtrlSingal 272 273 // Todo: summerize all difftest skip condition 274 csrOut.isPerfCnt := csrMod.io.out.bits.isPerfCnt && csrModOutValid && func =/= CSROpType.jmp 275 csrOut.fpu.frm := csrMod.io.status.fpState.frm.asUInt 276 csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt 277 csrOut.vpu.vxrm := csrMod.io.status.vecState.vxrm.asUInt 278 279 csrOut.isXRet := isXRetFlag 280 281 csrOut.trapTarget := csrMod.io.out.bits.targetPc 282 csrOut.interrupt := csrMod.io.status.interrupt 283 csrOut.wfi_event := csrMod.io.status.wfiEvent 284 285 csrOut.tlb := tlb 286 287 csrOut.debugMode := csrMod.io.status.debugMode 288 289 csrOut.customCtrl match { 290 case custom => 291 custom.l1I_pf_enable := csrMod.io.status.custom.l1I_pf_enable 292 custom.l2_pf_enable := csrMod.io.status.custom.l2_pf_enable 293 custom.l1D_pf_enable := csrMod.io.status.custom.l1D_pf_enable 294 custom.l1D_pf_train_on_hit := csrMod.io.status.custom.l1D_pf_train_on_hit 295 custom.l1D_pf_enable_agt := csrMod.io.status.custom.l1D_pf_enable_agt 296 custom.l1D_pf_enable_pht := csrMod.io.status.custom.l1D_pf_enable_pht 297 custom.l1D_pf_active_threshold := csrMod.io.status.custom.l1D_pf_active_threshold 298 custom.l1D_pf_active_stride := csrMod.io.status.custom.l1D_pf_active_stride 299 custom.l1D_pf_enable_stride := csrMod.io.status.custom.l1D_pf_enable_stride 300 custom.l2_pf_store_only := csrMod.io.status.custom.l2_pf_store_only 301 // ICache 302 custom.icache_parity_enable := csrMod.io.status.custom.icache_parity_enable 303 // Load violation predictor 304 custom.lvpred_disable := csrMod.io.status.custom.lvpred_disable 305 custom.no_spec_load := csrMod.io.status.custom.no_spec_load 306 custom.storeset_wait_store := csrMod.io.status.custom.storeset_wait_store 307 custom.storeset_no_fast_wakeup := csrMod.io.status.custom.storeset_no_fast_wakeup 308 custom.lvpred_timeout := csrMod.io.status.custom.lvpred_timeout 309 // Branch predictor 310 custom.bp_ctrl := csrMod.io.status.custom.bp_ctrl 311 // Memory Block 312 custom.sbuffer_threshold := csrMod.io.status.custom.sbuffer_threshold 313 custom.ldld_vio_check_enable := csrMod.io.status.custom.ldld_vio_check_enable 314 custom.soft_prefetch_enable := csrMod.io.status.custom.soft_prefetch_enable 315 custom.cache_error_enable := csrMod.io.status.custom.cache_error_enable 316 custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable 317 custom.hd_misalign_st_enable := csrMod.io.status.custom.hd_misalign_st_enable 318 custom.hd_misalign_ld_enable := csrMod.io.status.custom.hd_misalign_ld_enable 319 // Rename 320 custom.fusion_enable := csrMod.io.status.custom.fusion_enable 321 custom.wfi_enable := csrMod.io.status.custom.wfi_enable 322 // distribute csr write signal 323 // write to frontend and memory 324 custom.distribute_csr.w.valid := csrWen 325 custom.distribute_csr.w.bits.addr := addr 326 custom.distribute_csr.w.bits.data := wdata 327 // rename single step 328 custom.singlestep := csrMod.io.status.singleStepFlag 329 // trigger 330 custom.frontend_trigger := csrMod.io.status.frontendTrigger 331 custom.mem_trigger := csrMod.io.status.memTrigger 332 // virtual mode 333 custom.virtMode := csrMod.io.status.privState.V.asBool 334 } 335 336 csrToDecode := csrMod.io.toDecode 337} 338 339class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 340 val hartId = Input(UInt(8.W)) 341 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 342 val clintTime = Input(ValidIO(UInt(64.W))) 343} 344 345class CSRToDecode(implicit p: Parameters) extends XSBundle { 346 val illegalInst = new Bundle { 347 /** 348 * illegal sfence.vma, sinval.vma 349 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 350 */ 351 val sfenceVMA = Bool() 352 353 /** 354 * illegal sfence.w.inval sfence.inval.ir 355 * raise EX_II when isModeHU 356 */ 357 val sfencePart = Bool() 358 359 /** 360 * illegal hfence.gvma, hinval.gvma 361 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 362 * the condition is the same as sfenceVMA 363 */ 364 val hfenceGVMA = Bool() 365 366 /** 367 * illegal hfence.vvma, hinval.vvma 368 * raise EX_II when isModeHU 369 */ 370 val hfenceVVMA = Bool() 371 372 /** 373 * illegal hlv, hlvx, and hsv 374 * raise EX_II when isModeHU && hstatus.HU=0 375 */ 376 val hlsv = Bool() 377 378 /** 379 * decode all fp inst or all vecfp inst 380 * raise EX_II when FS=Off 381 */ 382 val fsIsOff = Bool() 383 384 /** 385 * decode all vec inst 386 * raise EX_II when VS=Off 387 */ 388 val vsIsOff = Bool() 389 390 /** 391 * illegal wfi 392 * raise EX_II when isModeHU || !isModeM && mstatus.TW=1 393 */ 394 val wfi = Bool() 395 396 /** 397 * frm reserved 398 * raise EX_II when frm.data > 4 399 */ 400 val frm = Bool() 401 } 402 val virtualInst = new Bundle { 403 /** 404 * illegal sfence.vma, svinval.vma 405 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 406 */ 407 val sfenceVMA = Bool() 408 409 /** 410 * illegal sfence.w.inval sfence.inval.ir 411 * raise EX_VI when isModeVU 412 */ 413 val sfencePart = Bool() 414 415 /** 416 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 417 * raise EX_VI when isModeVS || isModeVU 418 */ 419 val hfence = Bool() 420 421 /** 422 * illegal hlv, hlvx, and hsv 423 * raise EX_VI when isModeVS || isModeVU 424 */ 425 val hlsv = Bool() 426 427 /** 428 * illegal wfi 429 * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1 430 */ 431 val wfi = Bool() 432 } 433}