Backend: add Dispatch2IqFpImp

Merge branch 'master' into vlsu-merge-master-0504

Backend: add FpScheduler

Bump utility and disable ConstantIn by default (#2955)

* use BigInt for initValue of Constantin.createRecord
* use WITH_CONSTANTIN=1 to enable the ConstantIn plugin

Merge branch 'master' into vlsu-tmp-master

rv64v: add ignore oldvd judgement in issue queue
1. when the instruction depend on old vd, we cannot set the srctype to imm
2. when vl = 0, we cannot set the srctype to imm because the vd keep the ol

rv64v: add ignore oldvd judgement in issue queue
1. when the instruction depend on old vd, we cannot set the srctype to imm
2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value
3. when vl = vlmax, we can set srctype to imm when vta is not se

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Backend: add vector load border response

* The border response will be set success when the vector load uop pass to MemBlock like load

Backend,MemBlock: add uopIdx for vector load/store feedback

VLSU: add framework of vector store feedback

Backend: support vector load&store better

* Todo: add more IQs for vector load&store
* Todo: make vector memory inst issue out of order
* Todo: fix bugs

rv64v: set vs to dirty when running vector instructions (#2892)

rv64v: fix the logic of writing vtype for vsetvl instruction (#2875)

BackendParams: more readable port config check

Backend: vf instr add Og2 stage (#2810)

* Backend: vf instr add Og2 stage

* Update ExeUnitParams.scala

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Co-authored-by: zhanglyGit <[email protected]>

Backend: add solution for inst gpaddr

* Use ifu write gpaddr

Merge remote-tracking branch 'upstream/master' into tmp-master

TODO: add gpaddr data path from frontend to backend

RVH: fix the errors after git rebase

Configs: correct MaxHartIdBits (#2838)

Currently, many different lengths of HartId in Xiangshan, making it hard to
configure it to scale more than 16 cores since we have set 4bits somewhere.
This

Configs: correct MaxHartIdBits (#2838)

Currently, many different lengths of HartId in Xiangshan, making it hard to
configure it to scale more than 16 cores since we have set 4bits somewhere.
This commit corrects MaxHartIdBits in config and uses MaxHartIDBits where
it needs to get this solved.

Signed-off-by: Yangyu Chen <[email protected]>

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Backend: remove unused extra RF read ports, connect real commit vtype to VTypeGen

Backend: remove unused pcMem read for exu in CtrlBlock (moved to PcTargetMem (OG0))

DataPath, PcTargetMem: move target PC reading to datapath og0, and refactor PcTargetMemIO

Backend: add ren signal to SyncDataModuleTemplate

vconfig: fix difftest interface for vtype and vl

IssueQueue: remove vecStd, refactor iq params, remove unused mem blocked signals

rv64v: fix vxrm and frm connection for vector instructions