1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 23import utility.{Constantin, ZeroExt} 24import xiangshan._ 25import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 26import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 27import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 28import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 29import xiangshan.backend.datapath.WbConfig._ 30import xiangshan.backend.datapath._ 31import xiangshan.backend.dispatch.CoreDispatchTopDownIO 32import xiangshan.backend.exu.ExuBlock 33import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 34import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PerfCounterIO} 35import xiangshan.backend.issue.EntryBundles._ 36import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 37import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 38import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 39import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 40import scala.collection.mutable 41 42class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 43 with HasXSParameter { 44 45 override def shouldBeInlined: Boolean = false 46 47 // check read & write port config 48 params.configChecks 49 50 /* Only update the idx in mem-scheduler here 51 * Idx in other schedulers can be updated the same way if needed 52 * 53 * Also note that we filter out the 'stData issue-queues' when counting 54 */ 55 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 56 ibp.updateIdx(idx) 57 } 58 59 println(params.iqWakeUpParams) 60 61 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 62 schdCfg.bindBackendParam(params) 63 } 64 65 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 66 iqCfg.bindBackendParam(params) 67 } 68 69 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 70 exuCfg.bindBackendParam(params) 71 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 72 exuCfg.updateExuIdx(i) 73 } 74 75 println("[Backend] ExuConfigs:") 76 for (exuCfg <- params.allExuParams) { 77 val fuConfigs = exuCfg.fuConfigs 78 val wbPortConfigs = exuCfg.wbPortConfigs 79 val immType = exuCfg.immType 80 81 println("[Backend] " + 82 s"${exuCfg.name}: " + 83 (if (exuCfg.fakeUnit) "fake, " else "") + 84 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 85 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 86 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 87 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 88 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 89 s"srcReg(${exuCfg.numRegSrc})" 90 ) 91 require( 92 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 93 fuConfigs.map(_.writeIntRf).reduce(_ || _), 94 s"${exuCfg.name} int wb port has no priority" 95 ) 96 require( 97 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 98 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 99 s"${exuCfg.name} vec wb port has no priority" 100 ) 101 } 102 103 println(s"[Backend] all fu configs") 104 for (cfg <- FuConfig.allConfigs) { 105 println(s"[Backend] $cfg") 106 } 107 108 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 109 for ((port, seq) <- params.getRdPortParams(IntData())) { 110 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 111 } 112 113 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 114 for ((port, seq) <- params.getWbPortParams(IntData())) { 115 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 116 } 117 118 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 119 for ((port, seq) <- params.getRdPortParams(VecData())) { 120 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 121 } 122 123 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 124 for ((port, seq) <- params.getWbPortParams(VecData())) { 125 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 126 } 127 128 println(s"[Backend] Dispatch Configs:") 129 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 130 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 131 132 params.updateCopyPdestInfo 133 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 134 params.allExuParams.map(_.copyNum) 135 val ctrlBlock = LazyModule(new CtrlBlock(params)) 136 val pcTargetMem = LazyModule(new PcTargetMem(params)) 137 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 138 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 139 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 140 val dataPath = LazyModule(new DataPath(params)) 141 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 142 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 143 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 144 145 lazy val module = new BackendImp(this) 146} 147 148class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 149 with HasXSParameter { 150 implicit private val params = wrapper.params 151 152 val io = IO(new BackendIO()(p, wrapper.params)) 153 154 private val ctrlBlock = wrapper.ctrlBlock.module 155 private val pcTargetMem = wrapper.pcTargetMem.module 156 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 157 private val vfScheduler = wrapper.vfScheduler.get.module 158 private val memScheduler = wrapper.memScheduler.get.module 159 private val dataPath = wrapper.dataPath.module 160 private val intExuBlock = wrapper.intExuBlock.get.module 161 private val vfExuBlock = wrapper.vfExuBlock.get.module 162 private val og2ForVector = Module(new Og2ForVector(params)) 163 private val bypassNetwork = Module(new BypassNetwork) 164 private val wbDataPath = Module(new WbDataPath(params)) 165 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 166 167 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 168 intScheduler.io.toSchedulers.wakeupVec ++ 169 vfScheduler.io.toSchedulers.wakeupVec ++ 170 memScheduler.io.toSchedulers.wakeupVec 171 ).map(x => (x.bits.exuIdx, x)).toMap 172 173 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 174 175 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 176 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 177 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 178 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 179 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 180 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 181 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 182 183 private val og1CancelOH: UInt = dataPath.io.og1CancelOH 184 private val og0CancelOH: UInt = dataPath.io.og0CancelOH 185 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 186 187 ctrlBlock.io.IQValidNumVec := intScheduler.io.IQValidNumVec 188 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 189 ctrlBlock.io.frontend <> io.frontend 190 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 191 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 192 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 193 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 194 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 195 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 196 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 197 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 198 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 199 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 200 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 201 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 202 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 203 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 204 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 205 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 206 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 207 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 208 209 intScheduler.io.fromTop.hartId := io.fromTop.hartId 210 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 211 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 212 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 213 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 214 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 215 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 216 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 217 intScheduler.io.fromDataPath.og0Cancel := og0CancelOH 218 intScheduler.io.fromDataPath.og1Cancel := og1CancelOH 219 intScheduler.io.ldCancel := io.mem.ldCancel 220 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 221 222 memScheduler.io.fromTop.hartId := io.fromTop.hartId 223 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 224 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 225 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 226 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 227 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 228 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 229 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 230 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 231 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 232 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 233 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 234 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 235 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 236 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 237 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 238 sink.valid := source.valid 239 sink.bits := source.bits.robIdx 240 } 241 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 242 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 243 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 244 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 245 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 246 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 247 memScheduler.io.fromDataPath.og0Cancel := og0CancelOH 248 memScheduler.io.fromDataPath.og1Cancel := og1CancelOH 249 memScheduler.io.ldCancel := io.mem.ldCancel 250 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 251 252 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 253 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 254 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 255 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 256 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 257 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 258 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 259 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 260 vfScheduler.io.fromDataPath.og0Cancel := og0CancelOH 261 vfScheduler.io.fromDataPath.og1Cancel := og1CancelOH 262 vfScheduler.io.ldCancel := io.mem.ldCancel 263 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 264 vfScheduler.io.fromOg2.get := og2ForVector.io.toVfIQ 265 266 dataPath.io.hartId := io.fromTop.hartId 267 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 268 269 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 270 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 271 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 272 273 dataPath.io.ldCancel := io.mem.ldCancel 274 275 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 276 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 277 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 278 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 279 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 280 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 281 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 282 dataPath.io.debugVconfigRat.foreach(_ := ctrlBlock.io.debug_vconfig_rat.get) 283 284 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 285 og2ForVector.io.ldCancel := io.mem.ldCancel 286 og2ForVector.io.fromOg1NoReg <> dataPath.io.toFpExu 287 288 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 289 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfExu 290 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 291 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 292 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 293 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 294 295 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 296 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 297 s"io.mem.writeback(${io.mem.writeBack.size})" 298 ) 299 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 300 sink.valid := source.valid 301 sink.bits.pdest := source.bits.uop.pdest 302 sink.bits.data := source.bits.data 303 } 304 305 306 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 307 for (i <- 0 until intExuBlock.io.in.length) { 308 for (j <- 0 until intExuBlock.io.in(i).length) { 309 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 310 NewPipelineConnect( 311 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 312 Mux( 313 bypassNetwork.io.toExus.int(i)(j).fire, 314 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 315 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 316 ), 317 Option("intExuBlock2bypassNetwork") 318 ) 319 } 320 } 321 322 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 323 pcTargetMem.io.toDataPath <> dataPath.io.fromPcTargetMem 324 325 private val csrio = intExuBlock.io.csrio.get 326 csrio.hartId := io.fromTop.hartId 327 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 328 csrio.fpu.isIllegal := false.B // Todo: remove it 329 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 330 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 331 332 val debugVconfig = dataPath.io.debugVconfig match { 333 case Some(x) => dataPath.io.debugVconfig.get.asTypeOf(new VConfig) 334 case None => 0.U.asTypeOf(new VConfig) 335 } 336 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 337 val debugVl = debugVconfig.vl 338 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 339 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 340 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 341 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 342 //Todo here need change design 343 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 344 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 345 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 346 csrio.exception := ctrlBlock.io.robio.exception 347 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 348 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 349 csrio.externalInterrupt := io.fromTop.externalInterrupt 350 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 351 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 352 csrio.perf <> io.perf 353 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 354 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 355 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 356 private val fenceio = intExuBlock.io.fenceio.get 357 io.fenceio <> fenceio 358 fenceio.disableSfence := csrio.disableSfence 359 fenceio.disableHfenceg := csrio.disableHfenceg 360 fenceio.disableHfencev := csrio.disableHfencev 361 fenceio.virtMode := csrio.customCtrl.virtMode 362 363 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 364 for (i <- 0 until vfExuBlock.io.in.size) { 365 for (j <- 0 until vfExuBlock.io.in(i).size) { 366 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 367 NewPipelineConnect( 368 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 369 Mux( 370 bypassNetwork.io.toExus.vf(i)(j).fire, 371 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 372 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 373 ), 374 Option("vfExuBlock2bypassNetwork") 375 ) 376 377 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 378 } 379 } 380 381 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 382 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 383 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 384 385 wbDataPath.io.flush := ctrlBlock.io.redirect 386 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 387 wbDataPath.io.fromIntExu <> intExuBlock.io.out 388 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 389 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 390 sink.valid := source.valid 391 source.ready := sink.ready 392 sink.bits.data := source.bits.data 393 sink.bits.pdest := source.bits.uop.pdest 394 sink.bits.robIdx := source.bits.uop.robIdx 395 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 396 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 397 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 398 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 399 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 400 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 401 sink.bits.debug := source.bits.debug 402 sink.bits.debugInfo := source.bits.uop.debugInfo 403 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 404 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 405 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 406 sink.bits.vls.foreach(x => { 407 x.vdIdx := source.bits.vdIdx.get 408 x.vdIdxInField := source.bits.vdIdxInField.get 409 x.vpu := source.bits.uop.vpu 410 x.oldVdPsrc := source.bits.uop.psrc(2) 411 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 412 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 413 }) 414 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 415 } 416 417 // to mem 418 private val memIssueParams = params.memSchdParams.get.issueBlockParams 419 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 420 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 421 422 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 423 for (i <- toMem.indices) { 424 for (j <- toMem(i).indices) { 425 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 426 val issueTimeout = 427 if (memExuBlocksHasLDU(i)(j)) 428 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 429 else 430 false.B 431 432 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 433 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 434 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 435 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 436 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 437 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 438 } 439 440 NewPipelineConnect( 441 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 442 Mux( 443 bypassNetwork.io.toExus.mem(i)(j).fire, 444 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 445 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 446 ), 447 Option("bypassNetwork2toMemExus") 448 ) 449 450 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 451 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 452 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 453 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 454 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 455 } 456 } 457 } 458 459 io.mem.redirect := ctrlBlock.io.redirect 460 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 461 val enableMdp = Constantin.createRecord("EnableMdp", true.B)(0) 462 sink.valid := source.valid 463 source.ready := sink.ready 464 sink.bits.iqIdx := source.bits.iqIdx 465 sink.bits.isFirstIssue := source.bits.isFirstIssue 466 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 467 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 468 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 469 sink.bits.uop.fuType := source.bits.fuType 470 sink.bits.uop.fuOpType := source.bits.fuOpType 471 sink.bits.uop.imm := source.bits.imm 472 sink.bits.uop.robIdx := source.bits.robIdx 473 sink.bits.uop.pdest := source.bits.pdest 474 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 475 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 476 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 477 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 478 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 479 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 480 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 481 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 482 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 483 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 484 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 485 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 486 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 487 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 488 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 489 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 490 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 491 } 492 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 493 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 494 io.mem.tlbCsr := csrio.tlb 495 io.mem.csrCtrl := csrio.customCtrl 496 io.mem.sfence := fenceio.sfence 497 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 498 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 499 require(io.mem.loadPcRead.size == params.LduCnt) 500 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 501 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 502 ctrlBlock.io.memLdPcRead(i).vld := io.mem.issueLda(i).valid 503 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 504 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 505 } 506 507 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 508 storePcRead := ctrlBlock.io.memStPcRead(i).data 509 ctrlBlock.io.memStPcRead(i).vld := io.mem.issueSta(i).valid 510 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 511 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 512 } 513 514 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 515 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 516 ctrlBlock.io.memHyPcRead(i).vld := io.mem.issueHylda(i).valid 517 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 518 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 519 }) 520 521 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 522 523 // mem io 524 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 525 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 526 527 io.frontendSfence := fenceio.sfence 528 io.frontendTlbCsr := csrio.tlb 529 io.frontendCsrCtrl := csrio.customCtrl 530 531 io.tlb <> csrio.tlb 532 533 io.csrCustomCtrl := csrio.customCtrl 534 535 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 536 537 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 538 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 539 540 io.debugRolling := ctrlBlock.io.debugRolling 541 542 if(backendParams.debugEn) { 543 dontTouch(memScheduler.io) 544 dontTouch(dataPath.io.toMemExu) 545 dontTouch(wbDataPath.io.fromMemExu) 546 } 547} 548 549class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 550 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 551 val flippedLda = true 552 // params alias 553 private val LoadQueueSize = VirtualLoadQueueSize 554 // In/Out // Todo: split it into one-direction bundle 555 val lsqEnqIO = Flipped(new LsqEnqIO) 556 val robLsqIO = new RobLsqIO 557 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 558 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 559 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 560 val ldCancel = Vec(params.LdExuCnt, Flipped(new LoadCancelIO)) 561 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 562 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 563 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 564 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 565 // Input 566 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 567 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 568 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 569 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 570 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 571 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 572 573 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 574 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 575 val memoryViolation = Flipped(ValidIO(new Redirect)) 576 val exceptionAddr = Input(new Bundle { 577 val vaddr = UInt(VAddrBits.W) 578 val gpaddr = UInt(GPAddrBits.W) 579 }) 580 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 581 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 582 val sqDeqPtr = Input(new SqPtr) 583 val lqDeqPtr = Input(new LqPtr) 584 585 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 586 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 587 588 val lqCanAccept = Input(Bool()) 589 val sqCanAccept = Input(Bool()) 590 591 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 592 val stIssuePtr = Input(new SqPtr()) 593 594 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 595 596 val debugLS = Flipped(Output(new DebugLSIO)) 597 598 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 599 // Output 600 val redirect = ValidIO(new Redirect) // rob flush MemBlock 601 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 602 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 603 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 604 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 605 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 606 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 607 608 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 609 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 610 611 val tlbCsr = Output(new TlbCsrBundle) 612 val csrCtrl = Output(new CustomCSRCtrlIO) 613 val sfence = Output(new SfenceBundle) 614 val isStoreException = Output(Bool()) 615 val isVlsException = Output(Bool()) 616 617 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 618 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 619 issueSta ++ 620 issueHylda ++ issueHysta ++ 621 issueLda ++ 622 issueVldu ++ 623 issueStd 624 }.toSeq 625 626 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 627 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 628 writebackSta ++ 629 writebackHyuLda ++ writebackHyuSta ++ 630 writebackLda ++ 631 writebackVldu ++ 632 writebackStd 633 } 634} 635 636class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 637 val fromTop = new Bundle { 638 val hartId = Input(UInt(hartIdLen.W)) 639 val externalInterrupt = new ExternalInterruptIO 640 } 641 642 val toTop = new Bundle { 643 val cpuHalted = Output(Bool()) 644 } 645 646 val fenceio = new FenceIO 647 // Todo: merge these bundles into BackendFrontendIO 648 val frontend = Flipped(new FrontendToCtrlIO) 649 val frontendSfence = Output(new SfenceBundle) 650 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 651 val frontendTlbCsr = Output(new TlbCsrBundle) 652 // distributed csr write 653 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 654 655 val mem = new BackendMemIO 656 657 val perf = Input(new PerfCounterIO) 658 659 val tlb = Output(new TlbCsrBundle) 660 661 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 662 663 val debugTopDown = new Bundle { 664 val fromRob = new RobCoreTopDownIO 665 val fromCore = new CoreDispatchTopDownIO 666 } 667 val debugRolling = new RobDebugRollingIO 668} 669