1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 23import utility.{Constantin, ZeroExt} 24import xiangshan._ 25import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 26import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 27import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 28import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 29import xiangshan.backend.datapath.WbConfig._ 30import xiangshan.backend.datapath._ 31import xiangshan.backend.dispatch.CoreDispatchTopDownIO 32import xiangshan.backend.exu.ExuBlock 33import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 34import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PerfCounterIO} 35import xiangshan.backend.issue.EntryBundles._ 36import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerImpBase} 37import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 38import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 39import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 40import scala.collection.mutable 41 42class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 43 with HasXSParameter { 44 45 override def shouldBeInlined: Boolean = false 46 47 /* Only update the idx in mem-scheduler here 48 * Idx in other schedulers can be updated the same way if needed 49 * 50 * Also note that we filter out the 'stData issue-queues' when counting 51 */ 52 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 53 ibp.updateIdx(idx) 54 } 55 56 println(params.iqWakeUpParams) 57 58 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 59 schdCfg.bindBackendParam(params) 60 } 61 62 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 63 iqCfg.bindBackendParam(params) 64 } 65 66 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 67 exuCfg.bindBackendParam(params) 68 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 69 exuCfg.updateExuIdx(i) 70 } 71 72 println("[Backend] ExuConfigs:") 73 for (exuCfg <- params.allExuParams) { 74 val fuConfigs = exuCfg.fuConfigs 75 val wbPortConfigs = exuCfg.wbPortConfigs 76 val immType = exuCfg.immType 77 78 println("[Backend] " + 79 s"${exuCfg.name}: " + 80 (if (exuCfg.fakeUnit) "fake, " else "") + 81 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 82 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 83 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 84 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 85 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 86 s"srcReg(${exuCfg.numRegSrc})" 87 ) 88 require( 89 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 90 fuConfigs.map(_.writeIntRf).reduce(_ || _), 91 s"${exuCfg.name} int wb port has no priority" 92 ) 93 require( 94 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 95 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 96 s"${exuCfg.name} vec wb port has no priority" 97 ) 98 } 99 100 println(s"[Backend] all fu configs") 101 for (cfg <- FuConfig.allConfigs) { 102 println(s"[Backend] $cfg") 103 } 104 105 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 106 for ((port, seq) <- params.getRdPortParams(IntData())) { 107 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 108 } 109 110 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 111 for ((port, seq) <- params.getWbPortParams(IntData())) { 112 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 113 } 114 115 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 116 for ((port, seq) <- params.getRdPortParams(VecData())) { 117 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 118 } 119 120 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 121 for ((port, seq) <- params.getWbPortParams(VecData())) { 122 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 123 } 124 125 println(s"[Backend] Dispatch Configs:") 126 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 127 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 128 129 params.updateCopyPdestInfo 130 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 131 params.allExuParams.map(_.copyNum) 132 val ctrlBlock = LazyModule(new CtrlBlock(params)) 133 val pcTargetMem = LazyModule(new PcTargetMem(params)) 134 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 135 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 136 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 137 val dataPath = LazyModule(new DataPath(params)) 138 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 139 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 140 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 141 142 lazy val module = new BackendImp(this) 143} 144 145class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 146 with HasXSParameter { 147 implicit private val params = wrapper.params 148 149 val io = IO(new BackendIO()(p, wrapper.params)) 150 151 private val ctrlBlock = wrapper.ctrlBlock.module 152 private val pcTargetMem = wrapper.pcTargetMem.module 153 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 154 private val vfScheduler = wrapper.vfScheduler.get.module 155 private val memScheduler = wrapper.memScheduler.get.module 156 private val dataPath = wrapper.dataPath.module 157 private val intExuBlock = wrapper.intExuBlock.get.module 158 private val vfExuBlock = wrapper.vfExuBlock.get.module 159 private val og2ForVector = Module(new Og2ForVector(params)) 160 private val bypassNetwork = Module(new BypassNetwork) 161 private val wbDataPath = Module(new WbDataPath(params)) 162 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 163 164 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 165 intScheduler.io.toSchedulers.wakeupVec ++ 166 vfScheduler.io.toSchedulers.wakeupVec ++ 167 memScheduler.io.toSchedulers.wakeupVec 168 ).map(x => (x.bits.exuIdx, x)).toMap 169 170 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 171 172 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 173 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 174 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 175 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 176 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 177 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 178 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 179 180 private val og1CancelOH: UInt = dataPath.io.og1CancelOH 181 private val og0CancelOH: UInt = dataPath.io.og0CancelOH 182 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 183 184 ctrlBlock.io.IQValidNumVec := intScheduler.io.IQValidNumVec 185 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 186 ctrlBlock.io.frontend <> io.frontend 187 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 188 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 189 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 190 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 191 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 192 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 193 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 194 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 195 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 196 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 197 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 198 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 199 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 200 ctrlBlock.perfinfo := DontCare // TODO: Implement backend hpm 201 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 202 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 203 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 204 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 205 206 intScheduler.io.fromTop.hartId := io.fromTop.hartId 207 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 208 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 209 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 210 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 211 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 212 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 213 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 214 intScheduler.io.fromDataPath.og0Cancel := og0CancelOH 215 intScheduler.io.fromDataPath.og1Cancel := og1CancelOH 216 intScheduler.io.ldCancel := io.mem.ldCancel 217 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 218 219 memScheduler.io.fromTop.hartId := io.fromTop.hartId 220 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 221 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 222 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 223 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 224 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 225 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 226 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 227 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 228 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 229 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 230 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 231 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 232 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 233 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 234 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 235 sink.valid := source.valid 236 sink.bits := source.bits.robIdx 237 } 238 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 239 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 240 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 241 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 242 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 243 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 244 memScheduler.io.fromDataPath.og0Cancel := og0CancelOH 245 memScheduler.io.fromDataPath.og1Cancel := og1CancelOH 246 memScheduler.io.ldCancel := io.mem.ldCancel 247 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 248 249 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 250 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 251 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 252 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 253 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 254 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 255 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 256 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 257 vfScheduler.io.fromDataPath.og0Cancel := og0CancelOH 258 vfScheduler.io.fromDataPath.og1Cancel := og1CancelOH 259 vfScheduler.io.ldCancel := io.mem.ldCancel 260 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 261 vfScheduler.io.fromOg2.get := og2ForVector.io.toVfIQ 262 263 dataPath.io.hartId := io.fromTop.hartId 264 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 265 266 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 267 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 268 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 269 270 dataPath.io.ldCancel := io.mem.ldCancel 271 272 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 273 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 274 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 275 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 276 dataPath.io.debugIntRat .foreach(_ := ctrlBlock.io.debug_int_rat.get) 277 dataPath.io.debugFpRat .foreach(_ := ctrlBlock.io.debug_fp_rat.get) 278 dataPath.io.debugVecRat .foreach(_ := ctrlBlock.io.debug_vec_rat.get) 279 dataPath.io.debugVconfigRat.foreach(_ := ctrlBlock.io.debug_vconfig_rat.get) 280 281 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 282 og2ForVector.io.ldCancel := io.mem.ldCancel 283 og2ForVector.io.fromOg1NoReg <> dataPath.io.toFpExu 284 285 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 286 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfExu 287 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 288 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 289 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 290 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 291 292 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 293 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 294 s"io.mem.writeback(${io.mem.writeBack.size})" 295 ) 296 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 297 sink.valid := source.valid 298 sink.bits.pdest := source.bits.uop.pdest 299 sink.bits.data := source.bits.data 300 } 301 302 303 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 304 for (i <- 0 until intExuBlock.io.in.length) { 305 for (j <- 0 until intExuBlock.io.in(i).length) { 306 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 307 NewPipelineConnect( 308 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 309 Mux( 310 bypassNetwork.io.toExus.int(i)(j).fire, 311 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 312 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 313 ), 314 Option("intExuBlock2bypassNetwork") 315 ) 316 } 317 } 318 319 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 320 pcTargetMem.io.toDataPath <> dataPath.io.fromPcTargetMem 321 322 private val csrio = intExuBlock.io.csrio.get 323 csrio.hartId := io.fromTop.hartId 324 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 325 csrio.fpu.isIllegal := false.B // Todo: remove it 326 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 327 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 328 329 val debugVconfig = dataPath.io.debugVconfig match { 330 case Some(x) => dataPath.io.debugVconfig.get.asTypeOf(new VConfig) 331 case None => 0.U.asTypeOf(new VConfig) 332 } 333 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 334 val debugVl = debugVconfig.vl 335 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 336 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 337 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 338 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 339 //Todo here need change design 340 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 341 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 342 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 343 csrio.exception := ctrlBlock.io.robio.exception 344 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 345 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 346 csrio.externalInterrupt := io.fromTop.externalInterrupt 347 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 348 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 349 csrio.perf <> io.perf 350 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 351 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 352 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 353 private val fenceio = intExuBlock.io.fenceio.get 354 io.fenceio <> fenceio 355 fenceio.disableSfence := csrio.disableSfence 356 fenceio.disableHfenceg := csrio.disableHfenceg 357 fenceio.disableHfencev := csrio.disableHfencev 358 fenceio.virtMode := csrio.customCtrl.virtMode 359 360 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 361 for (i <- 0 until vfExuBlock.io.in.size) { 362 for (j <- 0 until vfExuBlock.io.in(i).size) { 363 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 364 NewPipelineConnect( 365 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 366 Mux( 367 bypassNetwork.io.toExus.vf(i)(j).fire, 368 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 369 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 370 ), 371 Option("vfExuBlock2bypassNetwork") 372 ) 373 374 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 375 } 376 } 377 378 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 379 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 380 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 381 382 wbDataPath.io.flush := ctrlBlock.io.redirect 383 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 384 wbDataPath.io.fromIntExu <> intExuBlock.io.out 385 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 386 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 387 sink.valid := source.valid 388 source.ready := sink.ready 389 sink.bits.data := source.bits.data 390 sink.bits.pdest := source.bits.uop.pdest 391 sink.bits.robIdx := source.bits.uop.robIdx 392 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 393 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 394 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 395 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 396 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 397 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 398 sink.bits.debug := source.bits.debug 399 sink.bits.debugInfo := source.bits.uop.debugInfo 400 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 401 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 402 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 403 sink.bits.vls.foreach(x => { 404 x.vdIdx := source.bits.vdIdx.get 405 x.vdIdxInField := source.bits.vdIdxInField.get 406 x.vpu := source.bits.uop.vpu 407 x.oldVdPsrc := source.bits.uop.psrc(2) 408 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 409 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 410 }) 411 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 412 } 413 414 // to mem 415 private val memIssueParams = params.memSchdParams.get.issueBlockParams 416 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 417 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 418 419 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 420 for (i <- toMem.indices) { 421 for (j <- toMem(i).indices) { 422 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 423 val issueTimeout = 424 if (memExuBlocksHasLDU(i)(j)) 425 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 426 else 427 false.B 428 429 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 430 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 431 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 432 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 433 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 434 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 435 } 436 437 NewPipelineConnect( 438 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 439 Mux( 440 bypassNetwork.io.toExus.mem(i)(j).fire, 441 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 442 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 443 ), 444 Option("bypassNetwork2toMemExus") 445 ) 446 447 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 448 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 449 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 450 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 451 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 452 } 453 } 454 } 455 456 io.mem.redirect := ctrlBlock.io.redirect 457 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 458 val enableMdp = Constantin.createRecord("EnableMdp", true.B)(0) 459 sink.valid := source.valid 460 source.ready := sink.ready 461 sink.bits.iqIdx := source.bits.iqIdx 462 sink.bits.isFirstIssue := source.bits.isFirstIssue 463 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 464 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 465 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 466 sink.bits.uop.fuType := source.bits.fuType 467 sink.bits.uop.fuOpType := source.bits.fuOpType 468 sink.bits.uop.imm := source.bits.imm 469 sink.bits.uop.robIdx := source.bits.robIdx 470 sink.bits.uop.pdest := source.bits.pdest 471 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 472 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 473 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 474 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 475 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 476 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 477 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 478 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 479 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 480 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 481 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 482 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 483 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 484 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 485 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 486 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 487 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 488 } 489 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 490 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 491 io.mem.tlbCsr := csrio.tlb 492 io.mem.csrCtrl := csrio.customCtrl 493 io.mem.sfence := fenceio.sfence 494 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 495 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 496 require(io.mem.loadPcRead.size == params.LduCnt) 497 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 498 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 499 ctrlBlock.io.memLdPcRead(i).vld := io.mem.issueLda(i).valid 500 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 501 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 502 } 503 504 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 505 storePcRead := ctrlBlock.io.memStPcRead(i).data 506 ctrlBlock.io.memStPcRead(i).vld := io.mem.issueSta(i).valid 507 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 508 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 509 } 510 511 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 512 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 513 ctrlBlock.io.memHyPcRead(i).vld := io.mem.issueHylda(i).valid 514 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 515 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 516 }) 517 518 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 519 520 // mem io 521 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 522 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 523 524 io.frontendSfence := fenceio.sfence 525 io.frontendTlbCsr := csrio.tlb 526 io.frontendCsrCtrl := csrio.customCtrl 527 528 io.tlb <> csrio.tlb 529 530 io.csrCustomCtrl := csrio.customCtrl 531 532 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 533 534 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 535 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 536 537 io.debugRolling := ctrlBlock.io.debugRolling 538 539 if(backendParams.debugEn) { 540 dontTouch(memScheduler.io) 541 dontTouch(dataPath.io.toMemExu) 542 dontTouch(wbDataPath.io.fromMemExu) 543 } 544} 545 546class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 547 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 548 val flippedLda = true 549 // params alias 550 private val LoadQueueSize = VirtualLoadQueueSize 551 // In/Out // Todo: split it into one-direction bundle 552 val lsqEnqIO = Flipped(new LsqEnqIO) 553 val robLsqIO = new RobLsqIO 554 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 555 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 556 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 557 val ldCancel = Vec(params.LdExuCnt, Flipped(new LoadCancelIO)) 558 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 559 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 560 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 561 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 562 // Input 563 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 564 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 565 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 566 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 567 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 568 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 569 570 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 571 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 572 val memoryViolation = Flipped(ValidIO(new Redirect)) 573 val exceptionAddr = Input(new Bundle { 574 val vaddr = UInt(VAddrBits.W) 575 val gpaddr = UInt(GPAddrBits.W) 576 }) 577 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 578 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 579 val sqDeqPtr = Input(new SqPtr) 580 val lqDeqPtr = Input(new LqPtr) 581 582 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 583 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 584 585 val lqCanAccept = Input(Bool()) 586 val sqCanAccept = Input(Bool()) 587 588 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 589 val stIssuePtr = Input(new SqPtr()) 590 591 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 592 593 val debugLS = Flipped(Output(new DebugLSIO)) 594 595 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 596 // Output 597 val redirect = ValidIO(new Redirect) // rob flush MemBlock 598 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 599 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 600 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 601 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 602 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 603 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 604 605 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 606 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 607 608 val tlbCsr = Output(new TlbCsrBundle) 609 val csrCtrl = Output(new CustomCSRCtrlIO) 610 val sfence = Output(new SfenceBundle) 611 val isStoreException = Output(Bool()) 612 val isVlsException = Output(Bool()) 613 614 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 615 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 616 issueSta ++ 617 issueHylda ++ issueHysta ++ 618 issueLda ++ 619 issueVldu ++ 620 issueStd 621 }.toSeq 622 623 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 624 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 625 writebackSta ++ 626 writebackHyuLda ++ writebackHyuSta ++ 627 writebackLda ++ 628 writebackVldu ++ 629 writebackStd 630 } 631} 632 633class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 634 val fromTop = new Bundle { 635 val hartId = Input(UInt(hartIdLen.W)) 636 val externalInterrupt = new ExternalInterruptIO 637 } 638 639 val toTop = new Bundle { 640 val cpuHalted = Output(Bool()) 641 } 642 643 val fenceio = new FenceIO 644 // Todo: merge these bundles into BackendFrontendIO 645 val frontend = Flipped(new FrontendToCtrlIO) 646 val frontendSfence = Output(new SfenceBundle) 647 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 648 val frontendTlbCsr = Output(new TlbCsrBundle) 649 // distributed csr write 650 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 651 652 val mem = new BackendMemIO 653 654 val perf = Input(new PerfCounterIO) 655 656 val tlb = Output(new TlbCsrBundle) 657 658 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 659 660 val debugTopDown = new Bundle { 661 val fromRob = new RobCoreTopDownIO 662 val fromCore = new CoreDispatchTopDownIO 663 } 664 val debugRolling = new RobDebugRollingIO 665} 666