l1tlb: tlb's req port can be configured to be block or non-blocked (#1656)

each tlb's port can be configured to be block or non-blocked.
For blocked port, there will be a req miss slot stored in tl

l1tlb: tlb's req port can be configured to be block or non-blocked (#1656)

each tlb's port can be configured to be block or non-blocked.
For blocked port, there will be a req miss slot stored in tlb, but belong to
core pipeline, which means only core pipeline flush will invalid them.

For another, itlb also use PTW Filter but with only 4 entries.
Last, keep svinval extension as usual, still work.


* tlb: add blocked-tlb support, miss frontend changes

* tlb: remove tlb's sameCycle support, result will return at next cycle

* tlb: remove param ShouldBlock, move block method into TLB module

* tlb: fix handle_block's miss_req logic

* mmu.filter: change filter's req.ready to canEnqueue

when filter can't let all the req enqueue, set the req.ready to false.
canEnqueue after filtering has long latency, so we use **_fake
without filtering, but the filter will still receive the reqs if
it can(after filtering).

* mmu.tlb: change name from BTlbPtwIO to VectorTlbPtwIO

* mmu: replace itlb's repeater to filter&repeaternb

* mmu.tlb: add TlbStorageWrapper to make TLB cleaner

more: BlockTlbRequestorIO is same with TlbRequestorIO, rm it

* mmu.tlb: rm unused param in function r_req_apply, fix syntax bug

* [WIP]icache: itlb usage from non-blocked to blocked

* mmu.tlb: change parameter NBWidth to Seq of boolean

* icache.mainpipe: fix itlb's resp.ready, not always true

* mmu.tlb: add kill sigal to blocked req that needs sync but fail

in frontend, icache,itlb,next pipe may not able to sync.
blocked tlb will store miss req ang blocks req, which makes itlb
couldn't work. So add kill logic to let itlb not to store reqs.

One more thing: fix icache's blocked tlb handling logic

* icache.mainpipe: fix tlb's ready_recv logic

icache mainpipe has two ports, but these two ports may not valid
all the same time. So add new signals tlb_need_recv to record whether
stage s1 should wait for the tlb.

* tlb: when flush, just set resp.valid and pf, pf for don't use it

* tlb: flush should concern satp.changed(for blocked io now)

* mmu.tlb: add new flush that doesn't flush reqs

Sfence.vma will flush inflight reqs and flushPipe
But some other sfence(svinval...) will not. So add new flush to
distinguish these two kinds of sfence signal

morw: forget to assign resp result when ptw back, fix it

* mmu.tlb: beautify miss_req_v and miss_v relative logic

* mmu.tlb: fix bug, when ptw back and bypass, concern level to genPPN

bug: when ptw back and bypass, forgot to concern level(1GB/2MB/4KB)
when genPPN.

by the way: some funtions need ": Unit = ", add it.

* mmu.filter: fix bug of canEnqueue, mixed with tlb_req and tlb.req

* icache.mainpipe: fix bug of tlbExcp's usage, & with tlb_need_back

Icache's mainpipe has two ports, but may only port 0 is valid.
When a port is invalid, the tlbexcp should be false.(Actually, should
be ignored).
So & tlb_need_back to fix this bug.

* sfence: instr in svinval ext will also flush pipe

A difficult problem to handle:
Sfence and Svinval will flush MMU, but only Sfence(some svinval)
will flush pipe. For itlb that some requestors are blocked and
icache doesn't recv flush for simplicity, itlb's blocked ptw req
should not be flushed.
It's a huge problem for MMU to handle for good or bad solutions. But
svinval is seldom used, so disable it's effiency.

* mmu: add parameter to control mmu's sfence delay latency

Difficult problem:
itlb's blocked req should not be abandoned, but sfence will flush
all infight reqs. when itlb and itlb repeater's delay is not same(itlb
is flushed, two cycles later, itlb repeater is flushed, then itlb's
ptw req after flushing will be also flushed sliently.
So add one parameter to control the flush delay to be the same.

* mmu.tlb: fix bug of csr.priv's delay & sfence valid when req fire

1. csr.priv's delay
csr.priv should not be delayed, csr.satp should be delayed.
for excep/intr will change csr.priv, which will be changed at one
instruction's (commit?). but csrrw satp will not, so satp has more
cycles to delay.
2. sfence
when sfence valid but blocked req fire, resp should still fire.
3. satp in TlbCsrBundle
let high bits of satp.ppn to be 0.U

* tlb&icache.mainpipe: rm commented codes

* mmu: move method genPPN to entry bundle

* l1tlb: divide l1tlb flush into flush_mmu and flush_pipe

Problem:
For l1tlb, there are blocked and non-blocked req ports.
For blocked ports, there are req slots to store missed reqs.
Some mmu flush like Sfence should not flush miss slots for outside
may still need get tlb resp, no matter wrong and correct resp.
For example. sfence will flush mmu and flush pipe, but won't flush
reqs inside icache, which waiting for tlb resp.
For example, svinval instr will flush mmu, but not flush pipe. so
tlb should return correct resp, althrough the ptw req is flushed
when tlb miss.

Solution:
divide l1tlb flush into flush_mmu and flush_pipe.
The req slot is considered to be a part of core pipeline and should
only be flushed by flush_pipe.
flush_mmu will flush mmu entries and inflight ptw reqs.
When miss but sfence flushed its ptw req, re-send.

* l1tlb: code clean, correct comments and rm unused codes

* l2tlb: divide filterSize into ifiterSize and dfilterSize

* l2tlb: prefetch req won't enter miss queue. Rename MSHR to missqueue

* l1tlb: when disable vm, ptw back should not bypass tlb and should let miss req go ahead

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dtlb: merge duplicated tlb together: one ld-tlb and one st-tlb. (#1654)

Old Edition:
2 ld tlb but with same entries. 2 st tlb but wih the same entries.
The 'duplicate' is used for timing optimizat

dtlb: merge duplicated tlb together: one ld-tlb and one st-tlb. (#1654)

Old Edition:
2 ld tlb but with same entries. 2 st tlb but wih the same entries.
The 'duplicate' is used for timing optimization that each tlb can
be placed close to mem access pipeline unit.

Problem:
The duplicate tlb takes more Power/Area.

New Edition:
Only 1 ld tlb and 1 st tlb now.
If the area is not ok, may merge ld and st together.

Fix: fix some syntax bug when changing parameters

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ldu: set load to use latency to 4 (#1623)

This commit adds an extra cycle for load pipeline. It should fix timing problem caused by load pipeline.
Huge perf loss is expected. Now load data result i

ldu: set load to use latency to 4 (#1623)

This commit adds an extra cycle for load pipeline. It should fix timing problem caused by load pipeline.
Huge perf loss is expected. Now load data result is sent to rs in load_s3, load may hit hint
(fastUop.valid) is sent to rs in load_s2.

We add a 3 cycle load to load fast forward data path. There should be enough time to forward
data inside memory block.

We will refactor code and add a load_s3 module in the future.

BREAKING CHANGE: load pipeline reorginized

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dcache: repipeline ecc check logic for timing (#1582)

This commit re-pipelines ECC check logic in data cache and exception generate logic for better timing.
Now ecc error is checked 1 cycle after r

dcache: repipeline ecc check logic for timing (#1582)

This commit re-pipelines ECC check logic in data cache and exception generate logic for better timing.
Now ecc error is checked 1 cycle after reading result from data sram. An extra cycle is added for load
writeback to ROB.

Future work: move the pipeline to https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/backend/CtrlBlock.scala#L266-L277, which add a regnext.

* dcache: repipeline ecc check logic for timing

* chore: fix normal loadAccessFault logic

* wbu: delay load unit wb for 1 cycle

* dcache: add 1 extra cycle for beu error report

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feat: parameterize load store (#1527)

* feat: parameterize load/store pipeline, etc.

* fix: use LoadPipelineWidth rather than LoadQueueSize

* fix: parameterize `rdataPtrExtNext`

* SBuffer:

feat: parameterize load store (#1527)

* feat: parameterize load/store pipeline, etc.

* fix: use LoadPipelineWidth rather than LoadQueueSize

* fix: parameterize `rdataPtrExtNext`

* SBuffer: fix idx update logic

* atomic: parameterize atomic logic in `MemBlock`

* StoreQueue: update allow enque requirement

* feat: support one load/store pipeline

* feat: parameterize `EnsbufferWidth`

* chore: resharp codes for better generated name

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parameters: reduce ghr length and make it calculated using a formula (#1442)

* parameters: reduce ghr length and make it calculated using a formula

* bpu: add error checking for ghist ptr, suppor

parameters: reduce ghr length and make it calculated using a formula (#1442)

* parameters: reduce ghr length and make it calculated using a formula

* bpu: add error checking for ghist ptr, support hist lengths that are not power of 2

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ICache : fix 2 potential rule violations according to TL specification (#1444)

* ReplacePipe: block miss until get ReleaseAck

* IPrefetch: cancle prefetch req when meet MSHR

* Fetch <perf>: ad

ICache : fix 2 potential rule violations according to TL specification (#1444)

* ReplacePipe: block miss until get ReleaseAck

* IPrefetch: cancle prefetch req when meet MSHR

* Fetch <perf>: add fetch bubble performance counters

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tage: recover to 4 tables

parameter: enable ghist diff and use optimized tage hist config

tage: use bim as altpred to reduce some levels of logic, introduce use_alt_on_na logic

ittage: use result in stage3

* remove base table and use ftb results as base pred
* add corrsponding redirect logic in bpu

tage: improve performance and reduce area

* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch pre

tage: improve performance and reduce area

* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch predictor components
in order to remove casting operation in composer

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bpu: timing optimizations

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* le

bpu: timing optimizations

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* left ras broken for the next commit to fix

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Merge remote-tracking branch 'origin/master' into bpu-timing

tage: timing optimizations

* reduce number of tables to 4, meanwhile quadrupling number of entries per table, improving area efficiency
* use per bank wrbypass
* invalidate read response when writin

tage: timing optimizations

* reduce number of tables to 4, meanwhile quadrupling number of entries per table, improving area efficiency
* use per bank wrbypass
* invalidate read response when writing to SRAM
* move validArray and useful bit into SRAMs, thus reducing area
* use an optimized history config for such table sizes

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ubtb: timing and performance optimizations

* timing: use single ported SRAMs, invalidating read responses on write
* performance:
-- shortening history length to accelerate training
-- use a predict

ubtb: timing and performance optimizations

* timing: use single ported SRAMs, invalidating read responses on write
* performance:
-- shortening history length to accelerate training
-- use a predictor to reduce s2_redirects on FTB not hit

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IPrefetch: add prefetch address merge and counter (#1404)

* fix performance counter in ICacheMainpipe

* IPrefetch: add prefetch address merge and counter

mem: implement lrsc backoff to survive in lr storm (#1383)

IPrefetch: fix prefetchPtr stop problem (#1387)

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be oc

IPrefetch: fix prefetchPtr stop problem (#1387)

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be occupied even when ICache miss

* Shut down IPrefetch

* IPrefetch: fix Hint not set PreferCache bit

* bump HuanCun

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tage-sc: merge two banks into one

IPrefetch: fix prefetchPtr stop problem (#1387)

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still b

IPrefetch: fix prefetchPtr stop problem (#1387)

* IPrefetch: fix prefetchPtr stop problem

* This problem happens because prefetchPtr still exits when close IPrefetch

* Fix PMP req port still be occupied even when ICache miss

* Shut down IPrefetch

* IPrefetch: fix Hint not set PreferCache bit

* bump HuanCun

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Merge remote-tracking branch 'origin/master' into bpu-timing

bpu: fix fallThruAddr on fallThruError, implement ghist diff mechanism

Add simple instruction prefetch for L2 (directed by branch prediction) (#1374)

* Add Naive Instruction Prefetch

* Add instruction prefetch module in ICache

* send Hint to L2 (prefetched data s

Add simple instruction prefetch for L2 (directed by branch prediction) (#1374)

* Add Naive Instruction Prefetch

* Add instruction prefetch module in ICache

* send Hint to L2 (prefetched data stores in L2)

* Ftq: add prefetchPtr and prefetch interface

* Fix IPrefetch PMP Port preempting problem

* Fix merge conflict

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dcache: let ecc error and l2 corrupt raise load af (#1369)

* dcache: let ecc error and l2 corrupt raise load af

If CSR.smblockctl.cache_error_enable is disabled, ecc error and l2 corrupt
will no

dcache: let ecc error and l2 corrupt raise load af (#1369)

* dcache: let ecc error and l2 corrupt raise load af

If CSR.smblockctl.cache_error_enable is disabled, ecc error and l2 corrupt
will not raise any exception.

* mem: enable cache error by default

* mem: support store ecc check, add ecc error csr

Support store / atom ecc check (early version)
Add ecc error csr to distingush ecc error and other access fault

Timing opt and unit tests to be added.

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