1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, MicroBTB, RAS, Tage, ITTage, Tage_SC} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableUBTB: Boolean = true, 64 HistoryLength: Int = 256, 65 EnableGHistDiff: Boolean = false, 66 UbtbSize: Int = 256, 67 FtbSize: Int = 2048, 68 RasSize: Int = 32, 69 CacheLineSize: Int = 512, 70 FtbWays: Int = 4, 71 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 72 // Sets Hist Tag 73 Seq(( 4096, 8, 12), 74 ( 4096, 13, 12), 75 ( 4096, 31, 12), 76 ( 4096, 119, 12)), 77 TageBanks: Int = 2, 78 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 79 // Sets Hist Tag 80 Seq(( 512, 0, 0), 81 ( 256, 4, 9), 82 ( 256, 8, 9), 83 ( 512, 13, 9), 84 ( 512, 16, 9), 85 ( 512, 31, 9)), 86 SCNRows: Int = 512, 87 SCNTables: Int = 4, 88 SCCtrBits: Int = 6, 89 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 90 numBr: Int = 2, 91 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 92 ((resp_in: BranchPredictionResp, p: Parameters) => { 93 // val loop = Module(new LoopPredictor) 94 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 95 // else Module(new Tage) } 96 // else { Module(new FakeTage) }) 97 val ftb = Module(new FTB()(p)) 98 val ubtb = Module(new MicroBTB()(p)) 99 val bim = Module(new BIM()(p)) 100 val tage = Module(new Tage_SC()(p)) 101 val ras = Module(new RAS()(p)) 102 val ittage = Module(new ITTage()(p)) 103 // val tage = Module(new Tage()(p)) 104 // val fake = Module(new FakePredictor()(p)) 105 106 // val preds = Seq(loop, tage, btb, ubtb, bim) 107 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 108 preds.map(_.io := DontCare) 109 110 // ubtb.io.resp_in(0) := resp_in 111 // bim.io.resp_in(0) := ubtb.io.resp 112 // btb.io.resp_in(0) := bim.io.resp 113 // tage.io.resp_in(0) := btb.io.resp 114 // loop.io.resp_in(0) := tage.io.resp 115 bim.io.in.bits.resp_in(0) := resp_in 116 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 117 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 118 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 119 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 120 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 121 122 (preds, ras.io.out.resp) 123 }), 124 IBufSize: Int = 48, 125 DecodeWidth: Int = 6, 126 RenameWidth: Int = 6, 127 CommitWidth: Int = 6, 128 FtqSize: Int = 64, 129 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 130 IssQueSize: Int = 16, 131 NRPhyRegs: Int = 192, 132 LoadQueueSize: Int = 80, 133 StoreQueueSize: Int = 64, 134 RobSize: Int = 256, 135 dpParams: DispatchParameters = DispatchParameters( 136 IntDqSize = 16, 137 FpDqSize = 16, 138 LsDqSize = 16, 139 IntDqDeqWidth = 4, 140 FpDqDeqWidth = 4, 141 LsDqDeqWidth = 4 142 ), 143 exuParameters: ExuParameters = ExuParameters( 144 JmpCnt = 1, 145 AluCnt = 4, 146 MulCnt = 0, 147 MduCnt = 2, 148 FmacCnt = 4, 149 FmiscCnt = 2, 150 FmiscDivSqrtCnt = 0, 151 LduCnt = 2, 152 StuCnt = 2 153 ), 154 LoadPipelineWidth: Int = 2, 155 StorePipelineWidth: Int = 2, 156 StoreBufferSize: Int = 16, 157 StoreBufferThreshold: Int = 7, 158 EnableLoadToLoadForward: Boolean = false, 159 EnableFastForward: Boolean = false, 160 EnableLdVioCheckAfterReset: Boolean = true, 161 EnableSoftPrefetchAfterReset: Boolean = true, 162 EnableCacheErrorAfterReset: Boolean = true, 163 RefillSize: Int = 512, 164 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 165 itlbParameters: TLBParameters = TLBParameters( 166 name = "itlb", 167 fetchi = true, 168 useDmode = false, 169 sameCycle = false, 170 missSameCycle = true, 171 normalNWays = 32, 172 normalReplacer = Some("plru"), 173 superNWays = 4, 174 superReplacer = Some("plru"), 175 shouldBlock = true 176 ), 177 ldtlbParameters: TLBParameters = TLBParameters( 178 name = "ldtlb", 179 normalNSets = 128, 180 normalNWays = 1, 181 normalAssociative = "sa", 182 normalReplacer = Some("setplru"), 183 superNWays = 8, 184 normalAsVictim = true, 185 outReplace = true, 186 partialStaticPMP = true, 187 saveLevel = true 188 ), 189 sttlbParameters: TLBParameters = TLBParameters( 190 name = "sttlb", 191 normalNSets = 128, 192 normalNWays = 1, 193 normalAssociative = "sa", 194 normalReplacer = Some("setplru"), 195 superNWays = 8, 196 normalAsVictim = true, 197 outReplace = true, 198 partialStaticPMP = true, 199 saveLevel = true 200 ), 201 refillBothTlb: Boolean = false, 202 btlbParameters: TLBParameters = TLBParameters( 203 name = "btlb", 204 normalNSets = 1, 205 normalNWays = 64, 206 superNWays = 4, 207 ), 208 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 209 NumPerfCounters: Int = 16, 210 icacheParameters: ICacheParameters = ICacheParameters( 211 tagECC = Some("parity"), 212 dataECC = Some("parity"), 213 replacer = Some("setplru"), 214 nMissEntries = 2, 215 nReleaseEntries = 2, 216 nProbeEntries = 2, 217 nPrefetchEntries = 4, 218 hasPrefetch = false, 219 ), 220 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 221 tagECC = Some("secded"), 222 dataECC = Some("secded"), 223 replacer = Some("setplru"), 224 nMissEntries = 16, 225 nProbeEntries = 8, 226 nReleaseEntries = 18 227 )), 228 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 229 name = "l2", 230 level = 2, 231 ways = 8, 232 sets = 1024, // default 512KB L2 233 prefetch = Some(huancun.prefetch.BOPParameters()) 234 )), 235 L2NBanks: Int = 1, 236 usePTWRepeater: Boolean = false, 237 softPTW: Boolean = false // dpi-c debug only 238){ 239 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 240 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 241 242 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 243 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 244 245 val fpExuConfigs = 246 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 247 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 248 249 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 250} 251 252case object DebugOptionsKey extends Field[DebugOptions] 253 254case class DebugOptions 255( 256 FPGAPlatform: Boolean = false, 257 EnableDifftest: Boolean = false, 258 AlwaysBasicDiff: Boolean = true, 259 EnableDebug: Boolean = false, 260 EnablePerfDebug: Boolean = true, 261 UseDRAMSim: Boolean = false 262) 263 264trait HasXSParameter { 265 266 implicit val p: Parameters 267 268 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 269 270 val coreParams = p(XSCoreParamsKey) 271 val env = p(DebugOptionsKey) 272 273 val XLEN = coreParams.XLEN 274 val minFLen = 32 275 val fLen = 64 276 def xLen = XLEN 277 278 val HasMExtension = coreParams.HasMExtension 279 val HasCExtension = coreParams.HasCExtension 280 val HasDiv = coreParams.HasDiv 281 val HasIcache = coreParams.HasICache 282 val HasDcache = coreParams.HasDCache 283 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 284 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 285 val AsidLength = coreParams.AsidLength 286 val AddrBytes = AddrBits / 8 // unused 287 val DataBits = XLEN 288 val DataBytes = DataBits / 8 289 val HasFPU = coreParams.HasFPU 290 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 291 val FetchWidth = coreParams.FetchWidth 292 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 293 val EnableBPU = coreParams.EnableBPU 294 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 295 val EnableRAS = coreParams.EnableRAS 296 val EnableLB = coreParams.EnableLB 297 val EnableLoop = coreParams.EnableLoop 298 val EnableSC = coreParams.EnableSC 299 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 300 val HistoryLength = coreParams.HistoryLength 301 val EnableGHistDiff = coreParams.EnableGHistDiff 302 val UbtbGHRLength = 4 303 val UbtbSize = coreParams.UbtbSize 304 val FtbSize = coreParams.FtbSize 305 val FtbWays = coreParams.FtbWays 306 val RasSize = coreParams.RasSize 307 308 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 309 coreParams.branchPredictor(resp_in, p) 310 } 311 val numBr = coreParams.numBr 312 val TageTableInfos = coreParams.TageTableInfos 313 314 315 val BankTageTableInfos = (0 until numBr).map(i => 316 TageTableInfos.map{ case (s, h, t) => (s/(1 << i), h, t) } 317 ) 318 val TageBanks = coreParams.TageBanks 319 val SCNRows = coreParams.SCNRows 320 val SCCtrBits = coreParams.SCCtrBits 321 val SCHistLens = coreParams.SCHistLens 322 val SCNTables = coreParams.SCNTables 323 324 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 325 case ((n, cb), h) => (n, cb, h) 326 } 327 val ITTageTableInfos = coreParams.ITTageTableInfos 328 type FoldedHistoryInfo = Tuple2[Int, Int] 329 val foldedGHistInfos = 330 (BankTageTableInfos.flatMap(_.map{ case (nRows, h, t) => 331 if (h > 0) 332 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 333 else 334 Set[FoldedHistoryInfo]() 335 }.reduce(_++_)).toSet ++ 336 SCTableInfos.map{ case (nRows, _, h) => 337 if (h > 0) 338 Set((h, min(log2Ceil(nRows/TageBanks), h))) 339 else 340 Set[FoldedHistoryInfo]() 341 }.reduce(_++_).toSet ++ 342 ITTageTableInfos.map{ case (nRows, h, t) => 343 if (h > 0) 344 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 345 else 346 Set[FoldedHistoryInfo]() 347 }.reduce(_++_) ++ 348 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 349 ).toList 350 351 val CacheLineSize = coreParams.CacheLineSize 352 val CacheLineHalfWord = CacheLineSize / 16 353 val ExtHistoryLength = HistoryLength + 64 354 val IBufSize = coreParams.IBufSize 355 val DecodeWidth = coreParams.DecodeWidth 356 val RenameWidth = coreParams.RenameWidth 357 val CommitWidth = coreParams.CommitWidth 358 val FtqSize = coreParams.FtqSize 359 val IssQueSize = coreParams.IssQueSize 360 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 361 val NRPhyRegs = coreParams.NRPhyRegs 362 val PhyRegIdxWidth = log2Up(NRPhyRegs) 363 val RobSize = coreParams.RobSize 364 val IntRefCounterWidth = log2Ceil(RobSize) 365 val LoadQueueSize = coreParams.LoadQueueSize 366 val StoreQueueSize = coreParams.StoreQueueSize 367 val dpParams = coreParams.dpParams 368 val exuParameters = coreParams.exuParameters 369 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 370 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 371 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 372 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 373 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 374 val LoadPipelineWidth = coreParams.LoadPipelineWidth 375 val StorePipelineWidth = coreParams.StorePipelineWidth 376 val StoreBufferSize = coreParams.StoreBufferSize 377 val StoreBufferThreshold = coreParams.StoreBufferThreshold 378 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 379 val EnableFastForward = coreParams.EnableFastForward 380 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 381 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 382 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 383 val RefillSize = coreParams.RefillSize 384 val asidLen = coreParams.MMUAsidLen 385 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 386 val refillBothTlb = coreParams.refillBothTlb 387 val itlbParams = coreParams.itlbParameters 388 val ldtlbParams = coreParams.ldtlbParameters 389 val sttlbParams = coreParams.sttlbParameters 390 val btlbParams = coreParams.btlbParameters 391 val l2tlbParams = coreParams.l2tlbParameters 392 val NumPerfCounters = coreParams.NumPerfCounters 393 394 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 395 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 396 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 397 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 398 399 val instBytes = if (HasCExtension) 2 else 4 400 val instOffsetBits = log2Ceil(instBytes) 401 402 val icacheParameters = coreParams.icacheParameters 403 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 404 405 val LRSCCycles = 100 406 407 // cache hierarchy configurations 408 val l1BusDataWidth = 256 409 410 // load violation predict 411 val ResetTimeMax2Pow = 20 //1078576 412 val ResetTimeMin2Pow = 10 //1024 413 // wait table parameters 414 val WaitTableSize = 1024 415 val MemPredPCWidth = log2Up(WaitTableSize) 416 val LWTUse2BitCounter = true 417 // store set parameters 418 val SSITSize = WaitTableSize 419 val LFSTSize = 32 420 val SSIDWidth = log2Up(LFSTSize) 421 val LFSTWidth = 4 422 val StoreSetEnable = true // LWT will be disabled if SS is enabled 423 424 val loadExuConfigs = coreParams.loadExuConfigs 425 val storeExuConfigs = coreParams.storeExuConfigs 426 427 val intExuConfigs = coreParams.intExuConfigs 428 429 val fpExuConfigs = coreParams.fpExuConfigs 430 431 val exuConfigs = coreParams.exuConfigs 432 433 val PCntIncrStep: Int = 6 434 val numPCntHc: Int = 25 435 val numPCntPtw: Int = 19 436 437 val numCSRPCntFrontend = 8 438 val numCSRPCntCtrl = 8 439 val numCSRPCntLsu = 8 440 val numCSRPCntHc = 5 441} 442