1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, MicroBTB, RAS, Tage, ITTage, Tage_SC} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableUBTB: Boolean = true, 64 HistoryLength: Int = 512, 65 EnableGHistDiff: Boolean = false, 66 UbtbSize: Int = 1024, 67 FtbSize: Int = 2048, 68 RasSize: Int = 32, 69 CacheLineSize: Int = 512, 70 FtbWays: Int = 4, 71 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 72 // Sets Hist Tag 73 Seq(( 128*8, 2, 10), 74 ( 128*8, 8, 10), 75 ( 128*8, 12, 10), 76 ( 128*8, 16, 10), 77 ( 128*8, 28, 10), 78 ( 128*8, 54, 10), 79 ( 128*8, 119, 10), 80 ( 128*8, 256, 10)), 81 TageBanks: Int = 2, 82 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 83 // Sets Hist Tag 84 Seq(( 512, 0, 0), 85 ( 256, 4, 9), 86 ( 256, 8, 9), 87 ( 512, 12, 9), 88 ( 512, 16, 9), 89 ( 512, 32, 9)), 90 SCNRows: Int = 512, 91 SCNTables: Int = 4, 92 SCCtrBits: Int = 6, 93 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 94 numBr: Int = 2, 95 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 96 ((resp_in: BranchPredictionResp, p: Parameters) => { 97 // val loop = Module(new LoopPredictor) 98 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 99 // else Module(new Tage) } 100 // else { Module(new FakeTage) }) 101 val ftb = Module(new FTB()(p)) 102 val ubtb = Module(new MicroBTB()(p)) 103 val bim = Module(new BIM()(p)) 104 val tage = Module(new Tage_SC()(p)) 105 val ras = Module(new RAS()(p)) 106 val ittage = Module(new ITTage()(p)) 107 // val tage = Module(new Tage()(p)) 108 // val fake = Module(new FakePredictor()(p)) 109 110 // val preds = Seq(loop, tage, btb, ubtb, bim) 111 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 112 preds.map(_.io := DontCare) 113 114 // ubtb.io.resp_in(0) := resp_in 115 // bim.io.resp_in(0) := ubtb.io.resp 116 // btb.io.resp_in(0) := bim.io.resp 117 // tage.io.resp_in(0) := btb.io.resp 118 // loop.io.resp_in(0) := tage.io.resp 119 bim.io.in.bits.resp_in(0) := resp_in 120 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 121 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 122 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 123 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 124 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 125 126 (preds, ras.io.out.resp) 127 }), 128 IBufSize: Int = 48, 129 DecodeWidth: Int = 6, 130 RenameWidth: Int = 6, 131 CommitWidth: Int = 6, 132 FtqSize: Int = 64, 133 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 134 IssQueSize: Int = 16, 135 NRPhyRegs: Int = 192, 136 LoadQueueSize: Int = 80, 137 StoreQueueSize: Int = 64, 138 RobSize: Int = 256, 139 dpParams: DispatchParameters = DispatchParameters( 140 IntDqSize = 16, 141 FpDqSize = 16, 142 LsDqSize = 16, 143 IntDqDeqWidth = 4, 144 FpDqDeqWidth = 4, 145 LsDqDeqWidth = 4 146 ), 147 exuParameters: ExuParameters = ExuParameters( 148 JmpCnt = 1, 149 AluCnt = 4, 150 MulCnt = 0, 151 MduCnt = 2, 152 FmacCnt = 4, 153 FmiscCnt = 2, 154 FmiscDivSqrtCnt = 0, 155 LduCnt = 2, 156 StuCnt = 2 157 ), 158 LoadPipelineWidth: Int = 2, 159 StorePipelineWidth: Int = 2, 160 StoreBufferSize: Int = 16, 161 StoreBufferThreshold: Int = 7, 162 EnableLoadToLoadForward: Boolean = false, 163 EnableFastForward: Boolean = false, 164 EnableLdVioCheckAfterReset: Boolean = true, 165 RefillSize: Int = 512, 166 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 167 itlbParameters: TLBParameters = TLBParameters( 168 name = "itlb", 169 fetchi = true, 170 useDmode = false, 171 sameCycle = false, 172 missSameCycle = true, 173 normalNWays = 32, 174 normalReplacer = Some("plru"), 175 superNWays = 4, 176 superReplacer = Some("plru"), 177 shouldBlock = true 178 ), 179 ldtlbParameters: TLBParameters = TLBParameters( 180 name = "ldtlb", 181 normalNSets = 128, 182 normalNWays = 1, 183 normalAssociative = "sa", 184 normalReplacer = Some("setplru"), 185 superNWays = 8, 186 normalAsVictim = true, 187 outReplace = true, 188 saveLevel = true 189 ), 190 sttlbParameters: TLBParameters = TLBParameters( 191 name = "sttlb", 192 normalNSets = 128, 193 normalNWays = 1, 194 normalAssociative = "sa", 195 normalReplacer = Some("setplru"), 196 superNWays = 8, 197 normalAsVictim = true, 198 outReplace = true, 199 saveLevel = true 200 ), 201 refillBothTlb: Boolean = false, 202 btlbParameters: TLBParameters = TLBParameters( 203 name = "btlb", 204 normalNSets = 1, 205 normalNWays = 64, 206 superNWays = 4, 207 ), 208 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 209 NumPerfCounters: Int = 16, 210 icacheParameters: ICacheParameters = ICacheParameters( 211 tagECC = Some("parity"), 212 dataECC = Some("parity"), 213 replacer = Some("setplru"), 214 nMissEntries = 2, 215 nReleaseEntries = 2 216 ), 217 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 218 tagECC = Some("secded"), 219 dataECC = Some("secded"), 220 replacer = Some("setplru"), 221 nMissEntries = 16, 222 nProbeEntries = 8, 223 nReleaseEntries = 18 224 )), 225 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 226 name = "l2", 227 level = 2, 228 ways = 8, 229 sets = 1024, // default 512KB L2 230 prefetch = Some(huancun.prefetch.BOPParameters()) 231 )), 232 L2NBanks: Int = 1, 233 usePTWRepeater: Boolean = false, 234 softPTW: Boolean = false // dpi-c debug only 235){ 236 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 237 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 238 239 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 240 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 241 242 val fpExuConfigs = 243 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 244 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 245 246 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 247} 248 249case object DebugOptionsKey extends Field[DebugOptions] 250 251case class DebugOptions 252( 253 FPGAPlatform: Boolean = false, 254 EnableDifftest: Boolean = false, 255 AlwaysBasicDiff: Boolean = true, 256 EnableDebug: Boolean = false, 257 EnablePerfDebug: Boolean = true, 258 UseDRAMSim: Boolean = false 259) 260 261trait HasXSParameter { 262 263 implicit val p: Parameters 264 265 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 266 267 val coreParams = p(XSCoreParamsKey) 268 val env = p(DebugOptionsKey) 269 270 val XLEN = coreParams.XLEN 271 val minFLen = 32 272 val fLen = 64 273 def xLen = XLEN 274 275 val HasMExtension = coreParams.HasMExtension 276 val HasCExtension = coreParams.HasCExtension 277 val HasDiv = coreParams.HasDiv 278 val HasIcache = coreParams.HasICache 279 val HasDcache = coreParams.HasDCache 280 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 281 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 282 val AsidLength = coreParams.AsidLength 283 val AddrBytes = AddrBits / 8 // unused 284 val DataBits = XLEN 285 val DataBytes = DataBits / 8 286 val HasFPU = coreParams.HasFPU 287 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 288 val FetchWidth = coreParams.FetchWidth 289 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 290 val EnableBPU = coreParams.EnableBPU 291 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 292 val EnableRAS = coreParams.EnableRAS 293 val EnableLB = coreParams.EnableLB 294 val EnableLoop = coreParams.EnableLoop 295 val EnableSC = coreParams.EnableSC 296 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 297 val HistoryLength = coreParams.HistoryLength 298 val EnableGHistDiff = coreParams.EnableGHistDiff 299 val UbtbGHRLength = log2Ceil(coreParams.UbtbSize) 300 val UbtbSize = coreParams.UbtbSize 301 val FtbSize = coreParams.FtbSize 302 val FtbWays = coreParams.FtbWays 303 val RasSize = coreParams.RasSize 304 305 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 306 coreParams.branchPredictor(resp_in, p) 307 } 308 val numBr = coreParams.numBr 309 val TageTableInfos = coreParams.TageTableInfos 310 311 312 val BankTageTableInfos = (0 until numBr).map(i => 313 TageTableInfos.map{ case (s, h, t) => (s/(1 << i), h, t) } 314 ) 315 val TageBanks = coreParams.TageBanks 316 val SCNRows = coreParams.SCNRows 317 val SCCtrBits = coreParams.SCCtrBits 318 val BankSCHistLens = Seq.fill(numBr)(coreParams.SCHistLens) 319 val BankSCNTables = Seq.fill(numBr)(coreParams.SCNTables) 320 321 val BankSCTableInfos = (BankSCNTables zip BankSCHistLens).map { 322 case (ntable, histlens) => 323 Seq.fill(ntable)((SCNRows, SCCtrBits)) zip histlens map {case ((n, cb), h) => (n, cb, h)} 324 } 325 val ITTageTableInfos = coreParams.ITTageTableInfos 326 type FoldedHistoryInfo = Tuple2[Int, Int] 327 val foldedGHistInfos = 328 (BankTageTableInfos.flatMap(_.map{ case (nRows, h, t) => 329 if (h > 0) 330 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 331 else 332 Set[FoldedHistoryInfo]() 333 }.reduce(_++_)).toSet ++ 334 BankSCTableInfos.flatMap(_.map{ case (nRows, _, h) => 335 if (h > 0) 336 Set((h, min(log2Ceil(nRows/TageBanks), h))) 337 else 338 Set[FoldedHistoryInfo]() 339 }.reduce(_++_)).toSet ++ 340 ITTageTableInfos.map{ case (nRows, h, t) => 341 if (h > 0) 342 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 343 else 344 Set[FoldedHistoryInfo]() 345 }.reduce(_++_) ++ 346 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 347 ).toList 348 349 val CacheLineSize = coreParams.CacheLineSize 350 val CacheLineHalfWord = CacheLineSize / 16 351 val ExtHistoryLength = HistoryLength + 64 352 val IBufSize = coreParams.IBufSize 353 val DecodeWidth = coreParams.DecodeWidth 354 val RenameWidth = coreParams.RenameWidth 355 val CommitWidth = coreParams.CommitWidth 356 val FtqSize = coreParams.FtqSize 357 val IssQueSize = coreParams.IssQueSize 358 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 359 val NRPhyRegs = coreParams.NRPhyRegs 360 val PhyRegIdxWidth = log2Up(NRPhyRegs) 361 val RobSize = coreParams.RobSize 362 val IntRefCounterWidth = log2Ceil(RobSize) 363 val LoadQueueSize = coreParams.LoadQueueSize 364 val StoreQueueSize = coreParams.StoreQueueSize 365 val dpParams = coreParams.dpParams 366 val exuParameters = coreParams.exuParameters 367 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 368 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 369 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 370 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 371 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 372 val LoadPipelineWidth = coreParams.LoadPipelineWidth 373 val StorePipelineWidth = coreParams.StorePipelineWidth 374 val StoreBufferSize = coreParams.StoreBufferSize 375 val StoreBufferThreshold = coreParams.StoreBufferThreshold 376 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 377 val EnableFastForward = coreParams.EnableFastForward 378 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 379 val RefillSize = coreParams.RefillSize 380 val asidLen = coreParams.MMUAsidLen 381 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 382 val refillBothTlb = coreParams.refillBothTlb 383 val itlbParams = coreParams.itlbParameters 384 val ldtlbParams = coreParams.ldtlbParameters 385 val sttlbParams = coreParams.sttlbParameters 386 val btlbParams = coreParams.btlbParameters 387 val l2tlbParams = coreParams.l2tlbParameters 388 val NumPerfCounters = coreParams.NumPerfCounters 389 390 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 391 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 392 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 393 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 394 395 val instBytes = if (HasCExtension) 2 else 4 396 val instOffsetBits = log2Ceil(instBytes) 397 398 val icacheParameters = coreParams.icacheParameters 399 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 400 401 val LRSCCycles = 100 402 403 // cache hierarchy configurations 404 val l1BusDataWidth = 256 405 406 // load violation predict 407 val ResetTimeMax2Pow = 20 //1078576 408 val ResetTimeMin2Pow = 10 //1024 409 // wait table parameters 410 val WaitTableSize = 1024 411 val MemPredPCWidth = log2Up(WaitTableSize) 412 val LWTUse2BitCounter = true 413 // store set parameters 414 val SSITSize = WaitTableSize 415 val LFSTSize = 32 416 val SSIDWidth = log2Up(LFSTSize) 417 val LFSTWidth = 4 418 val StoreSetEnable = true // LWT will be disabled if SS is enabled 419 420 val loadExuConfigs = coreParams.loadExuConfigs 421 val storeExuConfigs = coreParams.storeExuConfigs 422 423 val intExuConfigs = coreParams.intExuConfigs 424 425 val fpExuConfigs = coreParams.fpExuConfigs 426 427 val exuConfigs = coreParams.exuConfigs 428 429 val PCntIncrStep: Int = 6 430 val numPCntHc: Int = 25 431 val numPCntPtw: Int = 19 432 433 val numCSRPCntFrontend = 8 434 val numCSRPCntCtrl = 8 435 val numCSRPCntLsu = 8 436 val numCSRPCntHc = 5 437} 438