1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, MicroBTB, RAS, Tage, ITTage, Tage_SC} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableUBTB: Boolean = true, 64 HistoryLength: Int = 256, 65 EnableGHistDiff: Boolean = false, 66 UbtbSize: Int = 256, 67 FtbSize: Int = 2048, 68 RasSize: Int = 32, 69 CacheLineSize: Int = 512, 70 FtbWays: Int = 4, 71 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 72 // Sets Hist Tag 73 Seq(( 4096, 8, 8), 74 ( 4096, 13, 8), 75 ( 4096, 31, 8), 76 ( 4096, 119, 8)), 77 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 78 // Sets Hist Tag 79 Seq(( 256, 4, 9), 80 ( 256, 8, 9), 81 ( 512, 13, 9), 82 ( 512, 16, 9), 83 ( 512, 31, 9)), 84 SCNRows: Int = 512, 85 SCNTables: Int = 4, 86 SCCtrBits: Int = 6, 87 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 88 numBr: Int = 2, 89 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 90 ((resp_in: BranchPredictionResp, p: Parameters) => { 91 // val loop = Module(new LoopPredictor) 92 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 93 // else Module(new Tage) } 94 // else { Module(new FakeTage) }) 95 val ftb = Module(new FTB()(p)) 96 val ubtb = Module(new MicroBTB()(p)) 97 // val bim = Module(new BIM()(p)) 98 val tage = Module(new Tage_SC()(p)) 99 val ras = Module(new RAS()(p)) 100 val ittage = Module(new ITTage()(p)) 101 // val tage = Module(new Tage()(p)) 102 // val fake = Module(new FakePredictor()(p)) 103 104 // val preds = Seq(loop, tage, btb, ubtb, bim) 105 val preds = Seq(ubtb, tage, ftb, ittage, ras) 106 preds.map(_.io := DontCare) 107 108 // ubtb.io.resp_in(0) := resp_in 109 // bim.io.resp_in(0) := ubtb.io.resp 110 // btb.io.resp_in(0) := bim.io.resp 111 // tage.io.resp_in(0) := btb.io.resp 112 // loop.io.resp_in(0) := tage.io.resp 113 ubtb.io.in.bits.resp_in(0) := resp_in 114 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 115 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 116 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 117 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 118 119 (preds, ras.io.out.resp) 120 }), 121 IBufSize: Int = 48, 122 DecodeWidth: Int = 6, 123 RenameWidth: Int = 6, 124 CommitWidth: Int = 6, 125 FtqSize: Int = 64, 126 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 127 IssQueSize: Int = 16, 128 NRPhyRegs: Int = 192, 129 LoadQueueSize: Int = 80, 130 StoreQueueSize: Int = 64, 131 RobSize: Int = 256, 132 dpParams: DispatchParameters = DispatchParameters( 133 IntDqSize = 16, 134 FpDqSize = 16, 135 LsDqSize = 16, 136 IntDqDeqWidth = 4, 137 FpDqDeqWidth = 4, 138 LsDqDeqWidth = 4 139 ), 140 exuParameters: ExuParameters = ExuParameters( 141 JmpCnt = 1, 142 AluCnt = 4, 143 MulCnt = 0, 144 MduCnt = 2, 145 FmacCnt = 4, 146 FmiscCnt = 2, 147 FmiscDivSqrtCnt = 0, 148 LduCnt = 2, 149 StuCnt = 2 150 ), 151 LoadPipelineWidth: Int = 2, 152 StorePipelineWidth: Int = 2, 153 StoreBufferSize: Int = 16, 154 StoreBufferThreshold: Int = 7, 155 EnableLoadToLoadForward: Boolean = false, 156 EnableFastForward: Boolean = false, 157 EnableLdVioCheckAfterReset: Boolean = true, 158 EnableSoftPrefetchAfterReset: Boolean = true, 159 EnableCacheErrorAfterReset: Boolean = true, 160 RefillSize: Int = 512, 161 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 162 itlbParameters: TLBParameters = TLBParameters( 163 name = "itlb", 164 fetchi = true, 165 useDmode = false, 166 sameCycle = false, 167 missSameCycle = true, 168 normalNWays = 32, 169 normalReplacer = Some("plru"), 170 superNWays = 4, 171 superReplacer = Some("plru"), 172 shouldBlock = true 173 ), 174 ldtlbParameters: TLBParameters = TLBParameters( 175 name = "ldtlb", 176 normalNSets = 128, 177 normalNWays = 1, 178 normalAssociative = "sa", 179 normalReplacer = Some("setplru"), 180 superNWays = 8, 181 normalAsVictim = true, 182 outReplace = true, 183 partialStaticPMP = true, 184 saveLevel = true 185 ), 186 sttlbParameters: TLBParameters = TLBParameters( 187 name = "sttlb", 188 normalNSets = 128, 189 normalNWays = 1, 190 normalAssociative = "sa", 191 normalReplacer = Some("setplru"), 192 superNWays = 8, 193 normalAsVictim = true, 194 outReplace = true, 195 partialStaticPMP = true, 196 saveLevel = true 197 ), 198 refillBothTlb: Boolean = false, 199 btlbParameters: TLBParameters = TLBParameters( 200 name = "btlb", 201 normalNSets = 1, 202 normalNWays = 64, 203 superNWays = 4, 204 ), 205 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 206 NumPerfCounters: Int = 16, 207 icacheParameters: ICacheParameters = ICacheParameters( 208 tagECC = Some("parity"), 209 dataECC = Some("parity"), 210 replacer = Some("setplru"), 211 nMissEntries = 2, 212 nReleaseEntries = 2, 213 nProbeEntries = 2, 214 nPrefetchEntries = 2, 215 hasPrefetch = true, 216 ), 217 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 218 tagECC = Some("secded"), 219 dataECC = Some("secded"), 220 replacer = Some("setplru"), 221 nMissEntries = 16, 222 nProbeEntries = 8, 223 nReleaseEntries = 18 224 )), 225 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 226 name = "l2", 227 level = 2, 228 ways = 8, 229 sets = 1024, // default 512KB L2 230 prefetch = Some(huancun.prefetch.BOPParameters()) 231 )), 232 L2NBanks: Int = 1, 233 usePTWRepeater: Boolean = false, 234 softPTW: Boolean = false // dpi-c debug only 235){ 236 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 237 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 238 239 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 240 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 241 242 val fpExuConfigs = 243 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 244 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 245 246 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 247} 248 249case object DebugOptionsKey extends Field[DebugOptions] 250 251case class DebugOptions 252( 253 FPGAPlatform: Boolean = false, 254 EnableDifftest: Boolean = false, 255 AlwaysBasicDiff: Boolean = true, 256 EnableDebug: Boolean = false, 257 EnablePerfDebug: Boolean = true, 258 UseDRAMSim: Boolean = false 259) 260 261trait HasXSParameter { 262 263 implicit val p: Parameters 264 265 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 266 267 val coreParams = p(XSCoreParamsKey) 268 val env = p(DebugOptionsKey) 269 270 val XLEN = coreParams.XLEN 271 val minFLen = 32 272 val fLen = 64 273 def xLen = XLEN 274 275 val HasMExtension = coreParams.HasMExtension 276 val HasCExtension = coreParams.HasCExtension 277 val HasDiv = coreParams.HasDiv 278 val HasIcache = coreParams.HasICache 279 val HasDcache = coreParams.HasDCache 280 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 281 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 282 val AsidLength = coreParams.AsidLength 283 val AddrBytes = AddrBits / 8 // unused 284 val DataBits = XLEN 285 val DataBytes = DataBits / 8 286 val HasFPU = coreParams.HasFPU 287 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 288 val FetchWidth = coreParams.FetchWidth 289 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 290 val EnableBPU = coreParams.EnableBPU 291 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 292 val EnableRAS = coreParams.EnableRAS 293 val EnableLB = coreParams.EnableLB 294 val EnableLoop = coreParams.EnableLoop 295 val EnableSC = coreParams.EnableSC 296 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 297 val HistoryLength = coreParams.HistoryLength 298 val EnableGHistDiff = coreParams.EnableGHistDiff 299 val UbtbGHRLength = 4 300 val UbtbSize = coreParams.UbtbSize 301 val FtbSize = coreParams.FtbSize 302 val FtbWays = coreParams.FtbWays 303 val RasSize = coreParams.RasSize 304 305 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 306 coreParams.branchPredictor(resp_in, p) 307 } 308 val numBr = coreParams.numBr 309 val TageTableInfos = coreParams.TageTableInfos 310 val TageBanks = coreParams.numBr 311 val SCNRows = coreParams.SCNRows 312 val SCCtrBits = coreParams.SCCtrBits 313 val SCHistLens = coreParams.SCHistLens 314 val SCNTables = coreParams.SCNTables 315 316 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 317 case ((n, cb), h) => (n, cb, h) 318 } 319 val ITTageTableInfos = coreParams.ITTageTableInfos 320 type FoldedHistoryInfo = Tuple2[Int, Int] 321 val foldedGHistInfos = 322 (TageTableInfos.map{ case (nRows, h, t) => 323 if (h > 0) 324 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 325 else 326 Set[FoldedHistoryInfo]() 327 }.reduce(_++_).toSet ++ 328 SCTableInfos.map{ case (nRows, _, h) => 329 if (h > 0) 330 Set((h, min(log2Ceil(nRows/TageBanks), h))) 331 else 332 Set[FoldedHistoryInfo]() 333 }.reduce(_++_).toSet ++ 334 ITTageTableInfos.map{ case (nRows, h, t) => 335 if (h > 0) 336 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 337 else 338 Set[FoldedHistoryInfo]() 339 }.reduce(_++_) ++ 340 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 341 ).toList 342 343 val CacheLineSize = coreParams.CacheLineSize 344 val CacheLineHalfWord = CacheLineSize / 16 345 val ExtHistoryLength = HistoryLength + 64 346 val IBufSize = coreParams.IBufSize 347 val DecodeWidth = coreParams.DecodeWidth 348 val RenameWidth = coreParams.RenameWidth 349 val CommitWidth = coreParams.CommitWidth 350 val FtqSize = coreParams.FtqSize 351 val IssQueSize = coreParams.IssQueSize 352 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 353 val NRPhyRegs = coreParams.NRPhyRegs 354 val PhyRegIdxWidth = log2Up(NRPhyRegs) 355 val RobSize = coreParams.RobSize 356 val IntRefCounterWidth = log2Ceil(RobSize) 357 val LoadQueueSize = coreParams.LoadQueueSize 358 val StoreQueueSize = coreParams.StoreQueueSize 359 val dpParams = coreParams.dpParams 360 val exuParameters = coreParams.exuParameters 361 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 362 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 363 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 364 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 365 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 366 val LoadPipelineWidth = coreParams.LoadPipelineWidth 367 val StorePipelineWidth = coreParams.StorePipelineWidth 368 val StoreBufferSize = coreParams.StoreBufferSize 369 val StoreBufferThreshold = coreParams.StoreBufferThreshold 370 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 371 val EnableFastForward = coreParams.EnableFastForward 372 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 373 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 374 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 375 val RefillSize = coreParams.RefillSize 376 val asidLen = coreParams.MMUAsidLen 377 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 378 val refillBothTlb = coreParams.refillBothTlb 379 val itlbParams = coreParams.itlbParameters 380 val ldtlbParams = coreParams.ldtlbParameters 381 val sttlbParams = coreParams.sttlbParameters 382 val btlbParams = coreParams.btlbParameters 383 val l2tlbParams = coreParams.l2tlbParameters 384 val NumPerfCounters = coreParams.NumPerfCounters 385 386 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 387 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 388 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 389 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 390 391 val instBytes = if (HasCExtension) 2 else 4 392 val instOffsetBits = log2Ceil(instBytes) 393 394 val icacheParameters = coreParams.icacheParameters 395 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 396 397 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 398 // for constrained LR/SC loop 399 val LRSCCycles = 64 400 // for lr storm 401 val LRSCBackOff = 8 402 403 // cache hierarchy configurations 404 val l1BusDataWidth = 256 405 406 // load violation predict 407 val ResetTimeMax2Pow = 20 //1078576 408 val ResetTimeMin2Pow = 10 //1024 409 // wait table parameters 410 val WaitTableSize = 1024 411 val MemPredPCWidth = log2Up(WaitTableSize) 412 val LWTUse2BitCounter = true 413 // store set parameters 414 val SSITSize = WaitTableSize 415 val LFSTSize = 32 416 val SSIDWidth = log2Up(LFSTSize) 417 val LFSTWidth = 4 418 val StoreSetEnable = true // LWT will be disabled if SS is enabled 419 420 val loadExuConfigs = coreParams.loadExuConfigs 421 val storeExuConfigs = coreParams.storeExuConfigs 422 423 val intExuConfigs = coreParams.intExuConfigs 424 425 val fpExuConfigs = coreParams.fpExuConfigs 426 427 val exuConfigs = coreParams.exuConfigs 428 429 val PCntIncrStep: Int = 6 430 val numPCntHc: Int = 25 431 val numPCntPtw: Int = 19 432 433 val numCSRPCntFrontend = 8 434 val numCSRPCntCtrl = 8 435 val numCSRPCntLsu = 8 436 val numCSRPCntHc = 5 437} 438