1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, MicroBTB, RAS, Tage, ITTage, Tage_SC} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableUBTB: Boolean = true, 64 HistoryLength: Int = 256, 65 EnableGHistDiff: Boolean = false, 66 UbtbSize: Int = 256, 67 FtbSize: Int = 2048, 68 RasSize: Int = 32, 69 CacheLineSize: Int = 512, 70 FtbWays: Int = 4, 71 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 72 // Sets Hist Tag 73 Seq(( 4096, 8, 12), 74 ( 4096, 13, 12), 75 ( 4096, 31, 12), 76 ( 4096, 119, 12)), 77 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 78 // Sets Hist Tag 79 Seq(( 512, 0, 0), 80 ( 256, 4, 9), 81 ( 256, 8, 9), 82 ( 512, 13, 9), 83 ( 512, 16, 9), 84 ( 512, 31, 9)), 85 SCNRows: Int = 512, 86 SCNTables: Int = 4, 87 SCCtrBits: Int = 6, 88 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 89 numBr: Int = 2, 90 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 91 ((resp_in: BranchPredictionResp, p: Parameters) => { 92 // val loop = Module(new LoopPredictor) 93 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 94 // else Module(new Tage) } 95 // else { Module(new FakeTage) }) 96 val ftb = Module(new FTB()(p)) 97 val ubtb = Module(new MicroBTB()(p)) 98 val bim = Module(new BIM()(p)) 99 val tage = Module(new Tage_SC()(p)) 100 val ras = Module(new RAS()(p)) 101 val ittage = Module(new ITTage()(p)) 102 // val tage = Module(new Tage()(p)) 103 // val fake = Module(new FakePredictor()(p)) 104 105 // val preds = Seq(loop, tage, btb, ubtb, bim) 106 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 107 preds.map(_.io := DontCare) 108 109 // ubtb.io.resp_in(0) := resp_in 110 // bim.io.resp_in(0) := ubtb.io.resp 111 // btb.io.resp_in(0) := bim.io.resp 112 // tage.io.resp_in(0) := btb.io.resp 113 // loop.io.resp_in(0) := tage.io.resp 114 bim.io.in.bits.resp_in(0) := resp_in 115 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 116 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 117 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 118 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 119 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 120 121 (preds, ras.io.out.resp) 122 }), 123 IBufSize: Int = 48, 124 DecodeWidth: Int = 6, 125 RenameWidth: Int = 6, 126 CommitWidth: Int = 6, 127 FtqSize: Int = 64, 128 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 129 IssQueSize: Int = 16, 130 NRPhyRegs: Int = 192, 131 LoadQueueSize: Int = 80, 132 StoreQueueSize: Int = 64, 133 RobSize: Int = 256, 134 dpParams: DispatchParameters = DispatchParameters( 135 IntDqSize = 16, 136 FpDqSize = 16, 137 LsDqSize = 16, 138 IntDqDeqWidth = 4, 139 FpDqDeqWidth = 4, 140 LsDqDeqWidth = 4 141 ), 142 exuParameters: ExuParameters = ExuParameters( 143 JmpCnt = 1, 144 AluCnt = 4, 145 MulCnt = 0, 146 MduCnt = 2, 147 FmacCnt = 4, 148 FmiscCnt = 2, 149 FmiscDivSqrtCnt = 0, 150 LduCnt = 2, 151 StuCnt = 2 152 ), 153 LoadPipelineWidth: Int = 2, 154 StorePipelineWidth: Int = 2, 155 StoreBufferSize: Int = 16, 156 StoreBufferThreshold: Int = 7, 157 EnableLoadToLoadForward: Boolean = false, 158 EnableFastForward: Boolean = false, 159 EnableLdVioCheckAfterReset: Boolean = true, 160 EnableSoftPrefetchAfterReset: Boolean = true, 161 EnableCacheErrorAfterReset: Boolean = true, 162 RefillSize: Int = 512, 163 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 164 itlbParameters: TLBParameters = TLBParameters( 165 name = "itlb", 166 fetchi = true, 167 useDmode = false, 168 sameCycle = false, 169 missSameCycle = true, 170 normalNWays = 32, 171 normalReplacer = Some("plru"), 172 superNWays = 4, 173 superReplacer = Some("plru"), 174 shouldBlock = true 175 ), 176 ldtlbParameters: TLBParameters = TLBParameters( 177 name = "ldtlb", 178 normalNSets = 128, 179 normalNWays = 1, 180 normalAssociative = "sa", 181 normalReplacer = Some("setplru"), 182 superNWays = 8, 183 normalAsVictim = true, 184 outReplace = true, 185 partialStaticPMP = true, 186 saveLevel = true 187 ), 188 sttlbParameters: TLBParameters = TLBParameters( 189 name = "sttlb", 190 normalNSets = 128, 191 normalNWays = 1, 192 normalAssociative = "sa", 193 normalReplacer = Some("setplru"), 194 superNWays = 8, 195 normalAsVictim = true, 196 outReplace = true, 197 partialStaticPMP = true, 198 saveLevel = true 199 ), 200 refillBothTlb: Boolean = false, 201 btlbParameters: TLBParameters = TLBParameters( 202 name = "btlb", 203 normalNSets = 1, 204 normalNWays = 64, 205 superNWays = 4, 206 ), 207 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 208 NumPerfCounters: Int = 16, 209 icacheParameters: ICacheParameters = ICacheParameters( 210 tagECC = Some("parity"), 211 dataECC = Some("parity"), 212 replacer = Some("setplru"), 213 nMissEntries = 2, 214 nReleaseEntries = 2, 215 nProbeEntries = 2, 216 nPrefetchEntries = 2, 217 hasPrefetch = true, 218 ), 219 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 220 tagECC = Some("secded"), 221 dataECC = Some("secded"), 222 replacer = Some("setplru"), 223 nMissEntries = 16, 224 nProbeEntries = 8, 225 nReleaseEntries = 18 226 )), 227 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 228 name = "l2", 229 level = 2, 230 ways = 8, 231 sets = 1024, // default 512KB L2 232 prefetch = Some(huancun.prefetch.BOPParameters()) 233 )), 234 L2NBanks: Int = 1, 235 usePTWRepeater: Boolean = false, 236 softPTW: Boolean = false // dpi-c debug only 237){ 238 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 239 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 240 241 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 242 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 243 244 val fpExuConfigs = 245 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 246 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 247 248 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 249} 250 251case object DebugOptionsKey extends Field[DebugOptions] 252 253case class DebugOptions 254( 255 FPGAPlatform: Boolean = false, 256 EnableDifftest: Boolean = false, 257 AlwaysBasicDiff: Boolean = true, 258 EnableDebug: Boolean = false, 259 EnablePerfDebug: Boolean = true, 260 UseDRAMSim: Boolean = false 261) 262 263trait HasXSParameter { 264 265 implicit val p: Parameters 266 267 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 268 269 val coreParams = p(XSCoreParamsKey) 270 val env = p(DebugOptionsKey) 271 272 val XLEN = coreParams.XLEN 273 val minFLen = 32 274 val fLen = 64 275 def xLen = XLEN 276 277 val HasMExtension = coreParams.HasMExtension 278 val HasCExtension = coreParams.HasCExtension 279 val HasDiv = coreParams.HasDiv 280 val HasIcache = coreParams.HasICache 281 val HasDcache = coreParams.HasDCache 282 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 283 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 284 val AsidLength = coreParams.AsidLength 285 val AddrBytes = AddrBits / 8 // unused 286 val DataBits = XLEN 287 val DataBytes = DataBits / 8 288 val HasFPU = coreParams.HasFPU 289 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 290 val FetchWidth = coreParams.FetchWidth 291 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 292 val EnableBPU = coreParams.EnableBPU 293 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 294 val EnableRAS = coreParams.EnableRAS 295 val EnableLB = coreParams.EnableLB 296 val EnableLoop = coreParams.EnableLoop 297 val EnableSC = coreParams.EnableSC 298 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 299 val HistoryLength = coreParams.HistoryLength 300 val EnableGHistDiff = coreParams.EnableGHistDiff 301 val UbtbGHRLength = 4 302 val UbtbSize = coreParams.UbtbSize 303 val FtbSize = coreParams.FtbSize 304 val FtbWays = coreParams.FtbWays 305 val RasSize = coreParams.RasSize 306 307 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 308 coreParams.branchPredictor(resp_in, p) 309 } 310 val numBr = coreParams.numBr 311 val TageTableInfos = coreParams.TageTableInfos 312 313 314 val BankTageTableInfos = (0 until numBr).map(i => 315 TageTableInfos.map{ case (s, h, t) => (s/(1 << i), h, t) } 316 ) 317 val TageBanks = coreParams.numBr 318 val SCNRows = coreParams.SCNRows 319 val SCCtrBits = coreParams.SCCtrBits 320 val SCHistLens = coreParams.SCHistLens 321 val SCNTables = coreParams.SCNTables 322 323 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 324 case ((n, cb), h) => (n, cb, h) 325 } 326 val ITTageTableInfos = coreParams.ITTageTableInfos 327 type FoldedHistoryInfo = Tuple2[Int, Int] 328 val foldedGHistInfos = 329 (BankTageTableInfos.flatMap(_.map{ case (nRows, h, t) => 330 if (h > 0) 331 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 332 else 333 Set[FoldedHistoryInfo]() 334 }.reduce(_++_)).toSet ++ 335 SCTableInfos.map{ case (nRows, _, h) => 336 if (h > 0) 337 Set((h, min(log2Ceil(nRows/TageBanks), h))) 338 else 339 Set[FoldedHistoryInfo]() 340 }.reduce(_++_).toSet ++ 341 ITTageTableInfos.map{ case (nRows, h, t) => 342 if (h > 0) 343 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 344 else 345 Set[FoldedHistoryInfo]() 346 }.reduce(_++_) ++ 347 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 348 ).toList 349 350 val CacheLineSize = coreParams.CacheLineSize 351 val CacheLineHalfWord = CacheLineSize / 16 352 val ExtHistoryLength = HistoryLength + 64 353 val IBufSize = coreParams.IBufSize 354 val DecodeWidth = coreParams.DecodeWidth 355 val RenameWidth = coreParams.RenameWidth 356 val CommitWidth = coreParams.CommitWidth 357 val FtqSize = coreParams.FtqSize 358 val IssQueSize = coreParams.IssQueSize 359 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 360 val NRPhyRegs = coreParams.NRPhyRegs 361 val PhyRegIdxWidth = log2Up(NRPhyRegs) 362 val RobSize = coreParams.RobSize 363 val IntRefCounterWidth = log2Ceil(RobSize) 364 val LoadQueueSize = coreParams.LoadQueueSize 365 val StoreQueueSize = coreParams.StoreQueueSize 366 val dpParams = coreParams.dpParams 367 val exuParameters = coreParams.exuParameters 368 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 369 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 370 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 371 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 372 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 373 val LoadPipelineWidth = coreParams.LoadPipelineWidth 374 val StorePipelineWidth = coreParams.StorePipelineWidth 375 val StoreBufferSize = coreParams.StoreBufferSize 376 val StoreBufferThreshold = coreParams.StoreBufferThreshold 377 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 378 val EnableFastForward = coreParams.EnableFastForward 379 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 380 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 381 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 382 val RefillSize = coreParams.RefillSize 383 val asidLen = coreParams.MMUAsidLen 384 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 385 val refillBothTlb = coreParams.refillBothTlb 386 val itlbParams = coreParams.itlbParameters 387 val ldtlbParams = coreParams.ldtlbParameters 388 val sttlbParams = coreParams.sttlbParameters 389 val btlbParams = coreParams.btlbParameters 390 val l2tlbParams = coreParams.l2tlbParameters 391 val NumPerfCounters = coreParams.NumPerfCounters 392 393 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 394 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 395 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 396 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 397 398 val instBytes = if (HasCExtension) 2 else 4 399 val instOffsetBits = log2Ceil(instBytes) 400 401 val icacheParameters = coreParams.icacheParameters 402 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 403 404 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 405 // for constrained LR/SC loop 406 val LRSCCycles = 64 407 // for lr storm 408 val LRSCBackOff = 8 409 410 // cache hierarchy configurations 411 val l1BusDataWidth = 256 412 413 // load violation predict 414 val ResetTimeMax2Pow = 20 //1078576 415 val ResetTimeMin2Pow = 10 //1024 416 // wait table parameters 417 val WaitTableSize = 1024 418 val MemPredPCWidth = log2Up(WaitTableSize) 419 val LWTUse2BitCounter = true 420 // store set parameters 421 val SSITSize = WaitTableSize 422 val LFSTSize = 32 423 val SSIDWidth = log2Up(LFSTSize) 424 val LFSTWidth = 4 425 val StoreSetEnable = true // LWT will be disabled if SS is enabled 426 427 val loadExuConfigs = coreParams.loadExuConfigs 428 val storeExuConfigs = coreParams.storeExuConfigs 429 430 val intExuConfigs = coreParams.intExuConfigs 431 432 val fpExuConfigs = coreParams.fpExuConfigs 433 434 val exuConfigs = coreParams.exuConfigs 435 436 val PCntIncrStep: Int = 6 437 val numPCntHc: Int = 25 438 val numPCntPtw: Int = 19 439 440 val numCSRPCntFrontend = 8 441 val numCSRPCntCtrl = 8 442 val numCSRPCntLsu = 8 443 val numCSRPCntHc = 5 444} 445