1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, MicroBTB, RAS, Tage, ITTage, Tage_SC} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableUBTB: Boolean = true, 64 UbtbGHRLength: Int = 4, 65 HistoryLength: Int = 512, 66 EnableGHistDiff: Boolean = false, 67 UbtbSize: Int = 256, 68 FtbSize: Int = 2048, 69 RasSize: Int = 32, 70 CacheLineSize: Int = 512, 71 FtbWays: Int = 4, 72 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 73 // Sets Hist Tag 74 Seq(( 2048, 2, 8), 75 ( 2048, 8, 8), 76 ( 2048, 12, 8), 77 ( 2048, 13, 8), 78 ( 2048, 27, 8), 79 ( 2048, 54, 8), 80 ( 2048, 119, 8), 81 ( 2048, 256, 8)), 82 // Seq(( 4096, 8, 8), 83 // ( 4096, 13, 8), 84 // ( 4096, 31, 8), 85 // ( 4096, 119, 8)), 86 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 87 // Sets Hist Tag 88 Seq(( 256, 4, 9), 89 ( 256, 8, 9), 90 ( 512, 13, 9), 91 ( 512, 16, 9), 92 ( 512, 32, 9)), 93 SCNRows: Int = 512, 94 SCNTables: Int = 4, 95 SCCtrBits: Int = 6, 96 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 97 numBr: Int = 2, 98 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 99 ((resp_in: BranchPredictionResp, p: Parameters) => { 100 // val loop = Module(new LoopPredictor) 101 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 102 // else Module(new Tage) } 103 // else { Module(new FakeTage) }) 104 val ftb = Module(new FTB()(p)) 105 val ubtb = Module(new MicroBTB()(p)) 106 // val bim = Module(new BIM()(p)) 107 val tage = Module(new Tage_SC()(p)) 108 val ras = Module(new RAS()(p)) 109 val ittage = Module(new ITTage()(p)) 110 // val tage = Module(new Tage()(p)) 111 // val fake = Module(new FakePredictor()(p)) 112 113 // val preds = Seq(loop, tage, btb, ubtb, bim) 114 val preds = Seq(ubtb, tage, ftb, ittage, ras) 115 preds.map(_.io := DontCare) 116 117 // ubtb.io.resp_in(0) := resp_in 118 // bim.io.resp_in(0) := ubtb.io.resp 119 // btb.io.resp_in(0) := bim.io.resp 120 // tage.io.resp_in(0) := btb.io.resp 121 // loop.io.resp_in(0) := tage.io.resp 122 ubtb.io.in.bits.resp_in(0) := resp_in 123 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 124 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 125 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 126 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 127 128 (preds, ras.io.out.resp) 129 }), 130 IBufSize: Int = 48, 131 DecodeWidth: Int = 6, 132 RenameWidth: Int = 6, 133 CommitWidth: Int = 6, 134 FtqSize: Int = 64, 135 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 136 IssQueSize: Int = 16, 137 NRPhyRegs: Int = 192, 138 LoadQueueSize: Int = 80, 139 StoreQueueSize: Int = 64, 140 RobSize: Int = 256, 141 dpParams: DispatchParameters = DispatchParameters( 142 IntDqSize = 16, 143 FpDqSize = 16, 144 LsDqSize = 16, 145 IntDqDeqWidth = 4, 146 FpDqDeqWidth = 4, 147 LsDqDeqWidth = 4 148 ), 149 exuParameters: ExuParameters = ExuParameters( 150 JmpCnt = 1, 151 AluCnt = 4, 152 MulCnt = 0, 153 MduCnt = 2, 154 FmacCnt = 4, 155 FmiscCnt = 2, 156 FmiscDivSqrtCnt = 0, 157 LduCnt = 2, 158 StuCnt = 2 159 ), 160 LoadPipelineWidth: Int = 2, 161 StorePipelineWidth: Int = 2, 162 StoreBufferSize: Int = 16, 163 StoreBufferThreshold: Int = 7, 164 EnableLoadToLoadForward: Boolean = false, 165 EnableFastForward: Boolean = false, 166 EnableLdVioCheckAfterReset: Boolean = true, 167 EnableSoftPrefetchAfterReset: Boolean = true, 168 EnableCacheErrorAfterReset: Boolean = true, 169 RefillSize: Int = 512, 170 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 171 itlbParameters: TLBParameters = TLBParameters( 172 name = "itlb", 173 fetchi = true, 174 useDmode = false, 175 sameCycle = false, 176 missSameCycle = true, 177 normalNWays = 32, 178 normalReplacer = Some("plru"), 179 superNWays = 4, 180 superReplacer = Some("plru"), 181 shouldBlock = true 182 ), 183 ldtlbParameters: TLBParameters = TLBParameters( 184 name = "ldtlb", 185 normalNSets = 128, 186 normalNWays = 1, 187 normalAssociative = "sa", 188 normalReplacer = Some("setplru"), 189 superNWays = 8, 190 normalAsVictim = true, 191 outReplace = true, 192 partialStaticPMP = true, 193 saveLevel = true 194 ), 195 sttlbParameters: TLBParameters = TLBParameters( 196 name = "sttlb", 197 normalNSets = 128, 198 normalNWays = 1, 199 normalAssociative = "sa", 200 normalReplacer = Some("setplru"), 201 superNWays = 8, 202 normalAsVictim = true, 203 outReplace = true, 204 partialStaticPMP = true, 205 saveLevel = true 206 ), 207 refillBothTlb: Boolean = false, 208 btlbParameters: TLBParameters = TLBParameters( 209 name = "btlb", 210 normalNSets = 1, 211 normalNWays = 64, 212 superNWays = 4, 213 ), 214 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 215 NumPerfCounters: Int = 16, 216 icacheParameters: ICacheParameters = ICacheParameters( 217 tagECC = Some("parity"), 218 dataECC = Some("parity"), 219 replacer = Some("setplru"), 220 nMissEntries = 2, 221 nReleaseEntries = 2, 222 nProbeEntries = 2, 223 nPrefetchEntries = 2, 224 hasPrefetch = true, 225 ), 226 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 227 tagECC = Some("secded"), 228 dataECC = Some("secded"), 229 replacer = Some("setplru"), 230 nMissEntries = 16, 231 nProbeEntries = 8, 232 nReleaseEntries = 18 233 )), 234 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 235 name = "l2", 236 level = 2, 237 ways = 8, 238 sets = 1024, // default 512KB L2 239 prefetch = Some(huancun.prefetch.BOPParameters()) 240 )), 241 L2NBanks: Int = 1, 242 usePTWRepeater: Boolean = false, 243 softPTW: Boolean = false // dpi-c debug only 244){ 245 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 246 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 247 248 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 249 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 250 251 val fpExuConfigs = 252 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 253 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 254 255 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 256} 257 258case object DebugOptionsKey extends Field[DebugOptions] 259 260case class DebugOptions 261( 262 FPGAPlatform: Boolean = false, 263 EnableDifftest: Boolean = false, 264 AlwaysBasicDiff: Boolean = true, 265 EnableDebug: Boolean = false, 266 EnablePerfDebug: Boolean = true, 267 UseDRAMSim: Boolean = false 268) 269 270trait HasXSParameter { 271 272 implicit val p: Parameters 273 274 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 275 276 val coreParams = p(XSCoreParamsKey) 277 val env = p(DebugOptionsKey) 278 279 val XLEN = coreParams.XLEN 280 val minFLen = 32 281 val fLen = 64 282 def xLen = XLEN 283 284 val HasMExtension = coreParams.HasMExtension 285 val HasCExtension = coreParams.HasCExtension 286 val HasDiv = coreParams.HasDiv 287 val HasIcache = coreParams.HasICache 288 val HasDcache = coreParams.HasDCache 289 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 290 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 291 val AsidLength = coreParams.AsidLength 292 val AddrBytes = AddrBits / 8 // unused 293 val DataBits = XLEN 294 val DataBytes = DataBits / 8 295 val HasFPU = coreParams.HasFPU 296 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 297 val FetchWidth = coreParams.FetchWidth 298 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 299 val EnableBPU = coreParams.EnableBPU 300 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 301 val EnableRAS = coreParams.EnableRAS 302 val EnableLB = coreParams.EnableLB 303 val EnableLoop = coreParams.EnableLoop 304 val EnableSC = coreParams.EnableSC 305 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 306 val HistoryLength = coreParams.HistoryLength 307 val EnableGHistDiff = coreParams.EnableGHistDiff 308 val UbtbGHRLength = coreParams.UbtbGHRLength 309 val UbtbSize = coreParams.UbtbSize 310 val FtbSize = coreParams.FtbSize 311 val FtbWays = coreParams.FtbWays 312 val RasSize = coreParams.RasSize 313 314 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 315 coreParams.branchPredictor(resp_in, p) 316 } 317 val numBr = coreParams.numBr 318 val TageTableInfos = coreParams.TageTableInfos 319 val TageBanks = coreParams.numBr 320 val SCNRows = coreParams.SCNRows 321 val SCCtrBits = coreParams.SCCtrBits 322 val SCHistLens = coreParams.SCHistLens 323 val SCNTables = coreParams.SCNTables 324 325 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 326 case ((n, cb), h) => (n, cb, h) 327 } 328 val ITTageTableInfos = coreParams.ITTageTableInfos 329 type FoldedHistoryInfo = Tuple2[Int, Int] 330 val foldedGHistInfos = 331 (TageTableInfos.map{ case (nRows, h, t) => 332 if (h > 0) 333 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 334 else 335 Set[FoldedHistoryInfo]() 336 }.reduce(_++_).toSet ++ 337 SCTableInfos.map{ case (nRows, _, h) => 338 if (h > 0) 339 Set((h, min(log2Ceil(nRows/TageBanks), h))) 340 else 341 Set[FoldedHistoryInfo]() 342 }.reduce(_++_).toSet ++ 343 ITTageTableInfos.map{ case (nRows, h, t) => 344 if (h > 0) 345 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 346 else 347 Set[FoldedHistoryInfo]() 348 }.reduce(_++_) ++ 349 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 350 ).toList 351 352 val CacheLineSize = coreParams.CacheLineSize 353 val CacheLineHalfWord = CacheLineSize / 16 354 val ExtHistoryLength = HistoryLength + 64 355 val IBufSize = coreParams.IBufSize 356 val DecodeWidth = coreParams.DecodeWidth 357 val RenameWidth = coreParams.RenameWidth 358 val CommitWidth = coreParams.CommitWidth 359 val FtqSize = coreParams.FtqSize 360 val IssQueSize = coreParams.IssQueSize 361 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 362 val NRPhyRegs = coreParams.NRPhyRegs 363 val PhyRegIdxWidth = log2Up(NRPhyRegs) 364 val RobSize = coreParams.RobSize 365 val IntRefCounterWidth = log2Ceil(RobSize) 366 val LoadQueueSize = coreParams.LoadQueueSize 367 val StoreQueueSize = coreParams.StoreQueueSize 368 val dpParams = coreParams.dpParams 369 val exuParameters = coreParams.exuParameters 370 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 371 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 372 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 373 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 374 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 375 val LoadPipelineWidth = coreParams.LoadPipelineWidth 376 val StorePipelineWidth = coreParams.StorePipelineWidth 377 val StoreBufferSize = coreParams.StoreBufferSize 378 val StoreBufferThreshold = coreParams.StoreBufferThreshold 379 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 380 val EnableFastForward = coreParams.EnableFastForward 381 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 382 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 383 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 384 val RefillSize = coreParams.RefillSize 385 val asidLen = coreParams.MMUAsidLen 386 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 387 val refillBothTlb = coreParams.refillBothTlb 388 val itlbParams = coreParams.itlbParameters 389 val ldtlbParams = coreParams.ldtlbParameters 390 val sttlbParams = coreParams.sttlbParameters 391 val btlbParams = coreParams.btlbParameters 392 val l2tlbParams = coreParams.l2tlbParameters 393 val NumPerfCounters = coreParams.NumPerfCounters 394 395 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 396 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 397 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 398 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 399 400 val instBytes = if (HasCExtension) 2 else 4 401 val instOffsetBits = log2Ceil(instBytes) 402 403 val icacheParameters = coreParams.icacheParameters 404 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 405 406 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 407 // for constrained LR/SC loop 408 val LRSCCycles = 64 409 // for lr storm 410 val LRSCBackOff = 8 411 412 // cache hierarchy configurations 413 val l1BusDataWidth = 256 414 415 // load violation predict 416 val ResetTimeMax2Pow = 20 //1078576 417 val ResetTimeMin2Pow = 10 //1024 418 // wait table parameters 419 val WaitTableSize = 1024 420 val MemPredPCWidth = log2Up(WaitTableSize) 421 val LWTUse2BitCounter = true 422 // store set parameters 423 val SSITSize = WaitTableSize 424 val LFSTSize = 32 425 val SSIDWidth = log2Up(LFSTSize) 426 val LFSTWidth = 4 427 val StoreSetEnable = true // LWT will be disabled if SS is enabled 428 429 val loadExuConfigs = coreParams.loadExuConfigs 430 val storeExuConfigs = coreParams.storeExuConfigs 431 432 val intExuConfigs = coreParams.intExuConfigs 433 434 val fpExuConfigs = coreParams.fpExuConfigs 435 436 val exuConfigs = coreParams.exuConfigs 437 438 val PCntIncrStep: Int = 6 439 val numPCntHc: Int = 25 440 val numPCntPtw: Int = 19 441 442 val numCSRPCntFrontend = 8 443 val numCSRPCntCtrl = 8 444 val numCSRPCntLsu = 8 445 val numCSRPCntHc = 5 446} 447