1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, MicroBTB, RAS, Tage, ITTage, Tage_SC} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableUBTB: Boolean = true, 64 HistoryLength: Int = 512, 65 EnableGHistDiff: Boolean = false, 66 UbtbSize: Int = 1024, 67 FtbSize: Int = 2048, 68 RasSize: Int = 32, 69 CacheLineSize: Int = 512, 70 FtbWays: Int = 4, 71 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 72 // Sets Hist Tag 73 Seq(( 128*8, 2, 10), 74 ( 128*8, 8, 10), 75 ( 128*8, 12, 10), 76 ( 128*8, 16, 10), 77 ( 128*8, 28, 10), 78 ( 128*8, 54, 10), 79 ( 128*8, 119, 10), 80 ( 128*8, 256, 10)), 81 TageBanks: Int = 2, 82 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 83 // Sets Hist Tag 84 Seq(( 512, 0, 0), 85 ( 256, 4, 9), 86 ( 256, 8, 9), 87 ( 512, 12, 9), 88 ( 512, 16, 9), 89 ( 512, 32, 9)), 90 SCNRows: Int = 512, 91 SCNTables: Int = 4, 92 SCCtrBits: Int = 6, 93 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 94 numBr: Int = 2, 95 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 96 ((resp_in: BranchPredictionResp, p: Parameters) => { 97 // val loop = Module(new LoopPredictor) 98 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 99 // else Module(new Tage) } 100 // else { Module(new FakeTage) }) 101 val ftb = Module(new FTB()(p)) 102 val ubtb = Module(new MicroBTB()(p)) 103 val bim = Module(new BIM()(p)) 104 val tage = Module(new Tage_SC()(p)) 105 val ras = Module(new RAS()(p)) 106 val ittage = Module(new ITTage()(p)) 107 // val tage = Module(new Tage()(p)) 108 // val fake = Module(new FakePredictor()(p)) 109 110 // val preds = Seq(loop, tage, btb, ubtb, bim) 111 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 112 preds.map(_.io := DontCare) 113 114 // ubtb.io.resp_in(0) := resp_in 115 // bim.io.resp_in(0) := ubtb.io.resp 116 // btb.io.resp_in(0) := bim.io.resp 117 // tage.io.resp_in(0) := btb.io.resp 118 // loop.io.resp_in(0) := tage.io.resp 119 bim.io.in.bits.resp_in(0) := resp_in 120 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 121 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 122 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 123 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 124 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 125 126 (preds, ras.io.out.resp) 127 }), 128 IBufSize: Int = 48, 129 DecodeWidth: Int = 6, 130 RenameWidth: Int = 6, 131 CommitWidth: Int = 6, 132 FtqSize: Int = 64, 133 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 134 IssQueSize: Int = 16, 135 NRPhyRegs: Int = 192, 136 LoadQueueSize: Int = 80, 137 StoreQueueSize: Int = 64, 138 RobSize: Int = 256, 139 dpParams: DispatchParameters = DispatchParameters( 140 IntDqSize = 16, 141 FpDqSize = 16, 142 LsDqSize = 16, 143 IntDqDeqWidth = 4, 144 FpDqDeqWidth = 4, 145 LsDqDeqWidth = 4 146 ), 147 exuParameters: ExuParameters = ExuParameters( 148 JmpCnt = 1, 149 AluCnt = 4, 150 MulCnt = 0, 151 MduCnt = 2, 152 FmacCnt = 4, 153 FmiscCnt = 2, 154 FmiscDivSqrtCnt = 0, 155 LduCnt = 2, 156 StuCnt = 2 157 ), 158 LoadPipelineWidth: Int = 2, 159 StorePipelineWidth: Int = 2, 160 StoreBufferSize: Int = 16, 161 StoreBufferThreshold: Int = 7, 162 EnableLoadToLoadForward: Boolean = false, 163 EnableFastForward: Boolean = false, 164 EnableLdVioCheckAfterReset: Boolean = true, 165 EnableSoftPrefetchAfterReset: Boolean = true, 166 EnableCacheErrorAfterReset: Boolean = true, 167 RefillSize: Int = 512, 168 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 169 itlbParameters: TLBParameters = TLBParameters( 170 name = "itlb", 171 fetchi = true, 172 useDmode = false, 173 sameCycle = false, 174 missSameCycle = true, 175 normalNWays = 32, 176 normalReplacer = Some("plru"), 177 superNWays = 4, 178 superReplacer = Some("plru"), 179 shouldBlock = true 180 ), 181 ldtlbParameters: TLBParameters = TLBParameters( 182 name = "ldtlb", 183 normalNSets = 128, 184 normalNWays = 1, 185 normalAssociative = "sa", 186 normalReplacer = Some("setplru"), 187 superNWays = 8, 188 normalAsVictim = true, 189 outReplace = true, 190 partialStaticPMP = true, 191 saveLevel = true 192 ), 193 sttlbParameters: TLBParameters = TLBParameters( 194 name = "sttlb", 195 normalNSets = 128, 196 normalNWays = 1, 197 normalAssociative = "sa", 198 normalReplacer = Some("setplru"), 199 superNWays = 8, 200 normalAsVictim = true, 201 outReplace = true, 202 partialStaticPMP = true, 203 saveLevel = true 204 ), 205 refillBothTlb: Boolean = false, 206 btlbParameters: TLBParameters = TLBParameters( 207 name = "btlb", 208 normalNSets = 1, 209 normalNWays = 64, 210 superNWays = 4, 211 ), 212 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 213 NumPerfCounters: Int = 16, 214 icacheParameters: ICacheParameters = ICacheParameters( 215 tagECC = Some("parity"), 216 dataECC = Some("parity"), 217 replacer = Some("setplru"), 218 nMissEntries = 2, 219 nReleaseEntries = 2, 220 nProbeEntries = 2, 221 nPrefetchEntries = 4, 222 hasPrefetch = true, 223 ), 224 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 225 tagECC = Some("secded"), 226 dataECC = Some("secded"), 227 replacer = Some("setplru"), 228 nMissEntries = 16, 229 nProbeEntries = 8, 230 nReleaseEntries = 18 231 )), 232 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 233 name = "l2", 234 level = 2, 235 ways = 8, 236 sets = 1024, // default 512KB L2 237 prefetch = Some(huancun.prefetch.BOPParameters()) 238 )), 239 L2NBanks: Int = 1, 240 usePTWRepeater: Boolean = false, 241 softPTW: Boolean = false // dpi-c debug only 242){ 243 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 244 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 245 246 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 247 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 248 249 val fpExuConfigs = 250 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 251 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 252 253 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 254} 255 256case object DebugOptionsKey extends Field[DebugOptions] 257 258case class DebugOptions 259( 260 FPGAPlatform: Boolean = false, 261 EnableDifftest: Boolean = false, 262 AlwaysBasicDiff: Boolean = true, 263 EnableDebug: Boolean = false, 264 EnablePerfDebug: Boolean = true, 265 UseDRAMSim: Boolean = false 266) 267 268trait HasXSParameter { 269 270 implicit val p: Parameters 271 272 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 273 274 val coreParams = p(XSCoreParamsKey) 275 val env = p(DebugOptionsKey) 276 277 val XLEN = coreParams.XLEN 278 val minFLen = 32 279 val fLen = 64 280 def xLen = XLEN 281 282 val HasMExtension = coreParams.HasMExtension 283 val HasCExtension = coreParams.HasCExtension 284 val HasDiv = coreParams.HasDiv 285 val HasIcache = coreParams.HasICache 286 val HasDcache = coreParams.HasDCache 287 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 288 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 289 val AsidLength = coreParams.AsidLength 290 val AddrBytes = AddrBits / 8 // unused 291 val DataBits = XLEN 292 val DataBytes = DataBits / 8 293 val HasFPU = coreParams.HasFPU 294 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 295 val FetchWidth = coreParams.FetchWidth 296 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 297 val EnableBPU = coreParams.EnableBPU 298 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 299 val EnableRAS = coreParams.EnableRAS 300 val EnableLB = coreParams.EnableLB 301 val EnableLoop = coreParams.EnableLoop 302 val EnableSC = coreParams.EnableSC 303 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 304 val HistoryLength = coreParams.HistoryLength 305 val EnableGHistDiff = coreParams.EnableGHistDiff 306 val UbtbGHRLength = log2Ceil(coreParams.UbtbSize) 307 val UbtbSize = coreParams.UbtbSize 308 val FtbSize = coreParams.FtbSize 309 val FtbWays = coreParams.FtbWays 310 val RasSize = coreParams.RasSize 311 312 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 313 coreParams.branchPredictor(resp_in, p) 314 } 315 val numBr = coreParams.numBr 316 val TageTableInfos = coreParams.TageTableInfos 317 318 319 val BankTageTableInfos = (0 until numBr).map(i => 320 TageTableInfos.map{ case (s, h, t) => (s/(1 << i), h, t) } 321 ) 322 val TageBanks = coreParams.TageBanks 323 val SCNRows = coreParams.SCNRows 324 val SCCtrBits = coreParams.SCCtrBits 325 val BankSCHistLens = Seq.fill(numBr)(coreParams.SCHistLens) 326 val BankSCNTables = Seq.fill(numBr)(coreParams.SCNTables) 327 328 val BankSCTableInfos = (BankSCNTables zip BankSCHistLens).map { 329 case (ntable, histlens) => 330 Seq.fill(ntable)((SCNRows, SCCtrBits)) zip histlens map {case ((n, cb), h) => (n, cb, h)} 331 } 332 val ITTageTableInfos = coreParams.ITTageTableInfos 333 type FoldedHistoryInfo = Tuple2[Int, Int] 334 val foldedGHistInfos = 335 (BankTageTableInfos.flatMap(_.map{ case (nRows, h, t) => 336 if (h > 0) 337 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 338 else 339 Set[FoldedHistoryInfo]() 340 }.reduce(_++_)).toSet ++ 341 BankSCTableInfos.flatMap(_.map{ case (nRows, _, h) => 342 if (h > 0) 343 Set((h, min(log2Ceil(nRows/TageBanks), h))) 344 else 345 Set[FoldedHistoryInfo]() 346 }.reduce(_++_)).toSet ++ 347 ITTageTableInfos.map{ case (nRows, h, t) => 348 if (h > 0) 349 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 350 else 351 Set[FoldedHistoryInfo]() 352 }.reduce(_++_) ++ 353 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 354 ).toList 355 356 val CacheLineSize = coreParams.CacheLineSize 357 val CacheLineHalfWord = CacheLineSize / 16 358 val ExtHistoryLength = HistoryLength + 64 359 val IBufSize = coreParams.IBufSize 360 val DecodeWidth = coreParams.DecodeWidth 361 val RenameWidth = coreParams.RenameWidth 362 val CommitWidth = coreParams.CommitWidth 363 val FtqSize = coreParams.FtqSize 364 val IssQueSize = coreParams.IssQueSize 365 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 366 val NRPhyRegs = coreParams.NRPhyRegs 367 val PhyRegIdxWidth = log2Up(NRPhyRegs) 368 val RobSize = coreParams.RobSize 369 val IntRefCounterWidth = log2Ceil(RobSize) 370 val LoadQueueSize = coreParams.LoadQueueSize 371 val StoreQueueSize = coreParams.StoreQueueSize 372 val dpParams = coreParams.dpParams 373 val exuParameters = coreParams.exuParameters 374 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 375 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 376 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 377 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 378 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 379 val LoadPipelineWidth = coreParams.LoadPipelineWidth 380 val StorePipelineWidth = coreParams.StorePipelineWidth 381 val StoreBufferSize = coreParams.StoreBufferSize 382 val StoreBufferThreshold = coreParams.StoreBufferThreshold 383 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 384 val EnableFastForward = coreParams.EnableFastForward 385 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 386 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 387 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 388 val RefillSize = coreParams.RefillSize 389 val asidLen = coreParams.MMUAsidLen 390 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 391 val refillBothTlb = coreParams.refillBothTlb 392 val itlbParams = coreParams.itlbParameters 393 val ldtlbParams = coreParams.ldtlbParameters 394 val sttlbParams = coreParams.sttlbParameters 395 val btlbParams = coreParams.btlbParameters 396 val l2tlbParams = coreParams.l2tlbParameters 397 val NumPerfCounters = coreParams.NumPerfCounters 398 399 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 400 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 401 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 402 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 403 404 val instBytes = if (HasCExtension) 2 else 4 405 val instOffsetBits = log2Ceil(instBytes) 406 407 val icacheParameters = coreParams.icacheParameters 408 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 409 410 val LRSCCycles = 100 411 412 // cache hierarchy configurations 413 val l1BusDataWidth = 256 414 415 // load violation predict 416 val ResetTimeMax2Pow = 20 //1078576 417 val ResetTimeMin2Pow = 10 //1024 418 // wait table parameters 419 val WaitTableSize = 1024 420 val MemPredPCWidth = log2Up(WaitTableSize) 421 val LWTUse2BitCounter = true 422 // store set parameters 423 val SSITSize = WaitTableSize 424 val LFSTSize = 32 425 val SSIDWidth = log2Up(LFSTSize) 426 val LFSTWidth = 4 427 val StoreSetEnable = true // LWT will be disabled if SS is enabled 428 429 val loadExuConfigs = coreParams.loadExuConfigs 430 val storeExuConfigs = coreParams.storeExuConfigs 431 432 val intExuConfigs = coreParams.intExuConfigs 433 434 val fpExuConfigs = coreParams.fpExuConfigs 435 436 val exuConfigs = coreParams.exuConfigs 437 438 val PCntIncrStep: Int = 6 439 val numPCntHc: Int = 25 440 val numPCntPtw: Int = 19 441 442 val numCSRPCntFrontend = 8 443 val numCSRPCntCtrl = 8 444 val numCSRPCntLsu = 8 445 val numCSRPCntHc = 5 446} 447