1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, MicroBTB, RAS, Tage, ITTage, Tage_SC} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableUBTB: Boolean = true, 64 HistoryLength: Int = 256, 65 EnableGHistDiff: Boolean = false, 66 UbtbSize: Int = 256, 67 FtbSize: Int = 2048, 68 RasSize: Int = 32, 69 CacheLineSize: Int = 512, 70 FtbWays: Int = 4, 71 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 72 // Sets Hist Tag 73 Seq(( 4096, 8, 8), 74 ( 4096, 13, 8), 75 ( 4096, 31, 8), 76 ( 4096, 119, 8)), 77 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 78 // Sets Hist Tag 79 Seq(( 512, 0, 0), 80 ( 256, 4, 9), 81 ( 256, 8, 9), 82 ( 512, 13, 9), 83 ( 512, 16, 9), 84 ( 512, 31, 9)), 85 SCNRows: Int = 512, 86 SCNTables: Int = 4, 87 SCCtrBits: Int = 6, 88 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 89 numBr: Int = 2, 90 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 91 ((resp_in: BranchPredictionResp, p: Parameters) => { 92 // val loop = Module(new LoopPredictor) 93 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 94 // else Module(new Tage) } 95 // else { Module(new FakeTage) }) 96 val ftb = Module(new FTB()(p)) 97 val ubtb = Module(new MicroBTB()(p)) 98 // val bim = Module(new BIM()(p)) 99 val tage = Module(new Tage_SC()(p)) 100 val ras = Module(new RAS()(p)) 101 val ittage = Module(new ITTage()(p)) 102 // val tage = Module(new Tage()(p)) 103 // val fake = Module(new FakePredictor()(p)) 104 105 // val preds = Seq(loop, tage, btb, ubtb, bim) 106 val preds = Seq(ubtb, tage, ftb, ittage, ras) 107 preds.map(_.io := DontCare) 108 109 // ubtb.io.resp_in(0) := resp_in 110 // bim.io.resp_in(0) := ubtb.io.resp 111 // btb.io.resp_in(0) := bim.io.resp 112 // tage.io.resp_in(0) := btb.io.resp 113 // loop.io.resp_in(0) := tage.io.resp 114 ubtb.io.in.bits.resp_in(0) := resp_in 115 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 116 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 117 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 118 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 119 120 (preds, ras.io.out.resp) 121 }), 122 IBufSize: Int = 48, 123 DecodeWidth: Int = 6, 124 RenameWidth: Int = 6, 125 CommitWidth: Int = 6, 126 FtqSize: Int = 64, 127 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 128 IssQueSize: Int = 16, 129 NRPhyRegs: Int = 192, 130 LoadQueueSize: Int = 80, 131 StoreQueueSize: Int = 64, 132 RobSize: Int = 256, 133 dpParams: DispatchParameters = DispatchParameters( 134 IntDqSize = 16, 135 FpDqSize = 16, 136 LsDqSize = 16, 137 IntDqDeqWidth = 4, 138 FpDqDeqWidth = 4, 139 LsDqDeqWidth = 4 140 ), 141 exuParameters: ExuParameters = ExuParameters( 142 JmpCnt = 1, 143 AluCnt = 4, 144 MulCnt = 0, 145 MduCnt = 2, 146 FmacCnt = 4, 147 FmiscCnt = 2, 148 FmiscDivSqrtCnt = 0, 149 LduCnt = 2, 150 StuCnt = 2 151 ), 152 LoadPipelineWidth: Int = 2, 153 StorePipelineWidth: Int = 2, 154 StoreBufferSize: Int = 16, 155 StoreBufferThreshold: Int = 7, 156 EnableLoadToLoadForward: Boolean = false, 157 EnableFastForward: Boolean = false, 158 EnableLdVioCheckAfterReset: Boolean = true, 159 EnableSoftPrefetchAfterReset: Boolean = true, 160 EnableCacheErrorAfterReset: Boolean = true, 161 RefillSize: Int = 512, 162 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 163 itlbParameters: TLBParameters = TLBParameters( 164 name = "itlb", 165 fetchi = true, 166 useDmode = false, 167 sameCycle = false, 168 missSameCycle = true, 169 normalNWays = 32, 170 normalReplacer = Some("plru"), 171 superNWays = 4, 172 superReplacer = Some("plru"), 173 shouldBlock = true 174 ), 175 ldtlbParameters: TLBParameters = TLBParameters( 176 name = "ldtlb", 177 normalNSets = 128, 178 normalNWays = 1, 179 normalAssociative = "sa", 180 normalReplacer = Some("setplru"), 181 superNWays = 8, 182 normalAsVictim = true, 183 outReplace = true, 184 partialStaticPMP = true, 185 saveLevel = true 186 ), 187 sttlbParameters: TLBParameters = TLBParameters( 188 name = "sttlb", 189 normalNSets = 128, 190 normalNWays = 1, 191 normalAssociative = "sa", 192 normalReplacer = Some("setplru"), 193 superNWays = 8, 194 normalAsVictim = true, 195 outReplace = true, 196 partialStaticPMP = true, 197 saveLevel = true 198 ), 199 refillBothTlb: Boolean = false, 200 btlbParameters: TLBParameters = TLBParameters( 201 name = "btlb", 202 normalNSets = 1, 203 normalNWays = 64, 204 superNWays = 4, 205 ), 206 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 207 NumPerfCounters: Int = 16, 208 icacheParameters: ICacheParameters = ICacheParameters( 209 tagECC = Some("parity"), 210 dataECC = Some("parity"), 211 replacer = Some("setplru"), 212 nMissEntries = 2, 213 nReleaseEntries = 2, 214 nProbeEntries = 2, 215 nPrefetchEntries = 2, 216 hasPrefetch = true, 217 ), 218 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 219 tagECC = Some("secded"), 220 dataECC = Some("secded"), 221 replacer = Some("setplru"), 222 nMissEntries = 16, 223 nProbeEntries = 8, 224 nReleaseEntries = 18 225 )), 226 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 227 name = "l2", 228 level = 2, 229 ways = 8, 230 sets = 1024, // default 512KB L2 231 prefetch = Some(huancun.prefetch.BOPParameters()) 232 )), 233 L2NBanks: Int = 1, 234 usePTWRepeater: Boolean = false, 235 softPTW: Boolean = false // dpi-c debug only 236){ 237 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 238 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 239 240 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 241 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 242 243 val fpExuConfigs = 244 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 245 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 246 247 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 248} 249 250case object DebugOptionsKey extends Field[DebugOptions] 251 252case class DebugOptions 253( 254 FPGAPlatform: Boolean = false, 255 EnableDifftest: Boolean = false, 256 AlwaysBasicDiff: Boolean = true, 257 EnableDebug: Boolean = false, 258 EnablePerfDebug: Boolean = true, 259 UseDRAMSim: Boolean = false 260) 261 262trait HasXSParameter { 263 264 implicit val p: Parameters 265 266 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 267 268 val coreParams = p(XSCoreParamsKey) 269 val env = p(DebugOptionsKey) 270 271 val XLEN = coreParams.XLEN 272 val minFLen = 32 273 val fLen = 64 274 def xLen = XLEN 275 276 val HasMExtension = coreParams.HasMExtension 277 val HasCExtension = coreParams.HasCExtension 278 val HasDiv = coreParams.HasDiv 279 val HasIcache = coreParams.HasICache 280 val HasDcache = coreParams.HasDCache 281 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 282 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 283 val AsidLength = coreParams.AsidLength 284 val AddrBytes = AddrBits / 8 // unused 285 val DataBits = XLEN 286 val DataBytes = DataBits / 8 287 val HasFPU = coreParams.HasFPU 288 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 289 val FetchWidth = coreParams.FetchWidth 290 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 291 val EnableBPU = coreParams.EnableBPU 292 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 293 val EnableRAS = coreParams.EnableRAS 294 val EnableLB = coreParams.EnableLB 295 val EnableLoop = coreParams.EnableLoop 296 val EnableSC = coreParams.EnableSC 297 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 298 val HistoryLength = coreParams.HistoryLength 299 val EnableGHistDiff = coreParams.EnableGHistDiff 300 val UbtbGHRLength = 4 301 val UbtbSize = coreParams.UbtbSize 302 val FtbSize = coreParams.FtbSize 303 val FtbWays = coreParams.FtbWays 304 val RasSize = coreParams.RasSize 305 306 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 307 coreParams.branchPredictor(resp_in, p) 308 } 309 val numBr = coreParams.numBr 310 val TageTableInfos = coreParams.TageTableInfos 311 val TageBanks = coreParams.numBr 312 val SCNRows = coreParams.SCNRows 313 val SCCtrBits = coreParams.SCCtrBits 314 val SCHistLens = coreParams.SCHistLens 315 val SCNTables = coreParams.SCNTables 316 317 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 318 case ((n, cb), h) => (n, cb, h) 319 } 320 val ITTageTableInfos = coreParams.ITTageTableInfos 321 type FoldedHistoryInfo = Tuple2[Int, Int] 322 val foldedGHistInfos = 323 (TageTableInfos.map{ case (nRows, h, t) => 324 if (h > 0) 325 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 326 else 327 Set[FoldedHistoryInfo]() 328 }.reduce(_++_).toSet ++ 329 SCTableInfos.map{ case (nRows, _, h) => 330 if (h > 0) 331 Set((h, min(log2Ceil(nRows/TageBanks), h))) 332 else 333 Set[FoldedHistoryInfo]() 334 }.reduce(_++_).toSet ++ 335 ITTageTableInfos.map{ case (nRows, h, t) => 336 if (h > 0) 337 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 338 else 339 Set[FoldedHistoryInfo]() 340 }.reduce(_++_) ++ 341 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 342 ).toList 343 344 val CacheLineSize = coreParams.CacheLineSize 345 val CacheLineHalfWord = CacheLineSize / 16 346 val ExtHistoryLength = HistoryLength + 64 347 val IBufSize = coreParams.IBufSize 348 val DecodeWidth = coreParams.DecodeWidth 349 val RenameWidth = coreParams.RenameWidth 350 val CommitWidth = coreParams.CommitWidth 351 val FtqSize = coreParams.FtqSize 352 val IssQueSize = coreParams.IssQueSize 353 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 354 val NRPhyRegs = coreParams.NRPhyRegs 355 val PhyRegIdxWidth = log2Up(NRPhyRegs) 356 val RobSize = coreParams.RobSize 357 val IntRefCounterWidth = log2Ceil(RobSize) 358 val LoadQueueSize = coreParams.LoadQueueSize 359 val StoreQueueSize = coreParams.StoreQueueSize 360 val dpParams = coreParams.dpParams 361 val exuParameters = coreParams.exuParameters 362 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 363 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 364 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 365 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 366 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 367 val LoadPipelineWidth = coreParams.LoadPipelineWidth 368 val StorePipelineWidth = coreParams.StorePipelineWidth 369 val StoreBufferSize = coreParams.StoreBufferSize 370 val StoreBufferThreshold = coreParams.StoreBufferThreshold 371 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 372 val EnableFastForward = coreParams.EnableFastForward 373 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 374 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 375 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 376 val RefillSize = coreParams.RefillSize 377 val asidLen = coreParams.MMUAsidLen 378 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 379 val refillBothTlb = coreParams.refillBothTlb 380 val itlbParams = coreParams.itlbParameters 381 val ldtlbParams = coreParams.ldtlbParameters 382 val sttlbParams = coreParams.sttlbParameters 383 val btlbParams = coreParams.btlbParameters 384 val l2tlbParams = coreParams.l2tlbParameters 385 val NumPerfCounters = coreParams.NumPerfCounters 386 387 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 388 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 389 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 390 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 391 392 val instBytes = if (HasCExtension) 2 else 4 393 val instOffsetBits = log2Ceil(instBytes) 394 395 val icacheParameters = coreParams.icacheParameters 396 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 397 398 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 399 // for constrained LR/SC loop 400 val LRSCCycles = 64 401 // for lr storm 402 val LRSCBackOff = 8 403 404 // cache hierarchy configurations 405 val l1BusDataWidth = 256 406 407 // load violation predict 408 val ResetTimeMax2Pow = 20 //1078576 409 val ResetTimeMin2Pow = 10 //1024 410 // wait table parameters 411 val WaitTableSize = 1024 412 val MemPredPCWidth = log2Up(WaitTableSize) 413 val LWTUse2BitCounter = true 414 // store set parameters 415 val SSITSize = WaitTableSize 416 val LFSTSize = 32 417 val SSIDWidth = log2Up(LFSTSize) 418 val LFSTWidth = 4 419 val StoreSetEnable = true // LWT will be disabled if SS is enabled 420 421 val loadExuConfigs = coreParams.loadExuConfigs 422 val storeExuConfigs = coreParams.storeExuConfigs 423 424 val intExuConfigs = coreParams.intExuConfigs 425 426 val fpExuConfigs = coreParams.fpExuConfigs 427 428 val exuConfigs = coreParams.exuConfigs 429 430 val PCntIncrStep: Int = 6 431 val numPCntHc: Int = 25 432 val numPCntPtw: Int = 19 433 434 val numCSRPCntFrontend = 8 435 val numCSRPCntCtrl = 8 436 val numCSRPCntLsu = 8 437 val numCSRPCntHc = 5 438} 439