| #
c2afe453 |
| 30-Apr-2024 |
xiaofeibao <[email protected]> |
backend: fix STD read port
|
| #
ccfe8b43 |
| 29-Apr-2024 |
xiaofeibao <[email protected]> |
backend: int use independent fp writing port
|
| #
60f0c5ae |
| 26-Apr-2024 |
xiaofeibao <[email protected]> |
Backend: add FpScheduler
|
| #
dc5a9185 |
| 10-May-2024 |
Easton Man <[email protected]> |
bpu: clean up param and remove annoying print (#2958)
|
| #
ff74867b |
| 09-May-2024 |
Yangyu Chen <[email protected]> |
Parameters: replace val with def in trait HasXSParametes (#2952)
This will make FIR elaboration much faster.
Signed-off-by: Yangyu Chen <[email protected]>
|
| #
25df626e |
| 04-May-2024 |
good-circle <[email protected]> |
Merge branch 'master' into vlsu-tmp-master
|
| #
88884326 |
| 25-Apr-2024 |
weiding liu <[email protected]> |
VLSU: add suport of segment instruction
* segment Unit-Stride
* segment Stride
* segment order/unorder Index
TODO: except for order segment Index, other segment instruction can be executed out of or
VLSU: add suport of segment instruction
* segment Unit-Stride
* segment Stride
* segment order/unorder Index
TODO: except for order segment Index, other segment instruction can be executed out of order.
show more ...
|
| #
627be78b |
| 23-Apr-2024 |
good-circle <[email protected]> |
VLSU, lsq: support more than one vector pipeline
|
| #
b67f36d0 |
| 15-Apr-2024 |
xiaofeibao-xjtu <[email protected]> |
wakeup: add vfExu wakeup vfExu
|
| #
b2d6d8e7 |
| 09-Apr-2024 |
good-circle <[email protected]> |
VLSU: Add performance counters and parameters
|
| #
b7618691 |
| 29-Mar-2024 |
weiding liu <[email protected]> |
VLSU: fix bugs of build and connect
|
| #
3ea758f9 |
| 31-Mar-2024 |
Anzo <[email protected]> |
VLSU: fix allocated LSQ entries (#2829)
|
| #
6dbb4e08 |
| 28-Mar-2024 |
Xuan Hu <[email protected]> |
Backend: support vector load&store better
* Todo: add more IQs for vector load&store
* Todo: make vector memory inst issue out of order
* Todo: fix bugs
|
| #
26af847e |
| 25-Mar-2024 |
good-circle <[email protected]> |
rv64v: implement lsu & lsq vector datapath
|
| #
3952421b |
| 24-Mar-2024 |
weiding liu <[email protected]> |
rv64v: rewrite VLSU
uop split in V*SplitImp, flow merge in V*MergeBufferImp, uop issued out of order
|
| #
aee6a6d1 |
| 26-Apr-2024 |
Yanqin Li <[email protected]> |
l2bop: train by virtual address and buffer tlb req (#2382)
|
| #
ec49b127 |
| 19-Apr-2024 |
sinsanction <[email protected]> |
Backend: reduce the width of LoadDependency to 2 bits
|
| #
2e61107a |
| 20-Apr-2024 |
xiaofeibao <[email protected]> |
backend: change sta std read port, add 1 vfdiv
|
| #
24ff38fa |
| 17-Apr-2024 |
sinsanction <[email protected]> |
Parameters: update vfSchdParams to 3 IQ
|
| #
de111a36 |
| 07-Apr-2024 |
sinsanction <[email protected]> |
IssueQueue: add vf <-> mem fast wake up
|
| #
780712aa |
| 19-Mar-2024 |
xiaofeibao-xjtu <[email protected]> |
backend: new rob 8 banks read and 8 commit width
|
| #
c38df446 |
| 25-Mar-2024 |
zhanglyGit <[email protected]> |
Backend: vf instr add Og2 stage (#2810)
* Backend: vf instr add Og2 stage
* Update ExeUnitParams.scala
---------
Co-authored-by: zhanglyGit <[email protected]>
|
| #
f4b98c41 |
| 20-Mar-2024 |
sinsanction <[email protected]> |
Parameters: fix the count of vector read ports
|
| #
572278fa |
| 18-Mar-2024 |
Ziyue Zhang <[email protected]> |
float: use VCVT module for all fcvt instructions
Co-authored-by: chengguanghui <[email protected]>
|
| #
e25e4d90 |
| 11-Apr-2024 |
Xuan Hu <[email protected]> |
Merge remote-tracking branch 'upstream/master' into tmp-master
TODO: add gpaddr data path from frontend to backend
|