1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams, FakeIntPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import freechips.rocketchip.tile.MaxHartIdBits 42import system.SoCParamsKey 43import huancun._ 44import huancun.debug._ 45import xiangshan.cache.wpu.WPUParameters 46import coupledL2._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.min 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBits: Int = 39, 72 GPAddrBits: Int = 41, 73 HasFPU: Boolean = true, 74 HasVPU: Boolean = true, 75 HasCustomCSRCacheOp: Boolean = true, 76 FetchWidth: Int = 8, 77 AsidLength: Int = 16, 78 VmidLength: Int = 14, 79 EnableBPU: Boolean = true, 80 EnableBPD: Boolean = true, 81 EnableRAS: Boolean = true, 82 EnableLB: Boolean = false, 83 EnableLoop: Boolean = true, 84 EnableSC: Boolean = true, 85 EnbaleTlbDebug: Boolean = false, 86 EnableClockGate: Boolean = true, 87 EnableJal: Boolean = false, 88 EnableFauFTB: Boolean = true, 89 UbtbGHRLength: Int = 4, 90 // HistoryLength: Int = 512, 91 EnableGHistDiff: Boolean = true, 92 EnableCommitGHistDiff: Boolean = true, 93 UbtbSize: Int = 256, 94 FtbSize: Int = 2048, 95 RasSize: Int = 16, 96 RasSpecSize: Int = 32, 97 RasCtrSize: Int = 3, 98 CacheLineSize: Int = 512, 99 FtbWays: Int = 4, 100 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 101 // Sets Hist Tag 102 Seq(( 4096, 8, 8), 103 ( 4096, 13, 8), 104 ( 4096, 32, 8), 105 ( 4096, 119, 8)), 106 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 107 // Sets Hist Tag 108 Seq(( 256, 4, 9), 109 ( 256, 8, 9), 110 ( 512, 13, 9), 111 ( 512, 16, 9), 112 ( 512, 32, 9)), 113 SCNRows: Int = 512, 114 SCNTables: Int = 4, 115 SCCtrBits: Int = 6, 116 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 117 numBr: Int = 2, 118 branchPredictor: (BranchPredictionResp, Parameters) => Tuple2[Seq[BasePredictor], BranchPredictionResp] = 119 (resp_in: BranchPredictionResp, p: Parameters) => { 120 val ftb = Module(new FTB()(p)) 121 val uftb = Module(new FauFTB()(p)) 122 val tage = Module(new Tage_SC()(p)) 123 val ras = Module(new RAS()(p)) 124 val ittage = Module(new ITTage()(p)) 125 val preds = Seq(uftb, tage, ftb, ittage, ras) 126 preds.map(_.io := DontCare) 127 128 uftb.io.in.bits.resp_in(0) := resp_in 129 tage.io.in.bits.resp_in(0) := uftb.io.out 130 ftb.io.in.bits.resp_in(0) := tage.io.out 131 ittage.io.in.bits.resp_in(0) := ftb.io.out 132 ras.io.in.bits.resp_in(0) := ittage.io.out 133 134 (preds, ras.io.out) 135 }, 136 ICacheECCForceError: Boolean = false, 137 IBufSize: Int = 48, 138 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 139 DecodeWidth: Int = 6, 140 RenameWidth: Int = 6, 141 CommitWidth: Int = 8, 142 RobCommitWidth: Int = 8, 143 RabCommitWidth: Int = 6, 144 MaxUopSize: Int = 65, 145 EnableRenameSnapshot: Boolean = true, 146 RenameSnapshotNum: Int = 4, 147 FtqSize: Int = 64, 148 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 149 IntLogicRegs: Int = 32, 150 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 151 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 152 VCONFIG_IDX: Int = 32, 153 NRPhyRegs: Int = 192, 154 VirtualLoadQueueSize: Int = 72, 155 LoadQueueRARSize: Int = 72, 156 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 157 RollbackGroupSize: Int = 8, 158 LoadQueueReplaySize: Int = 72, 159 LoadUncacheBufferSize: Int = 20, 160 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 161 StoreQueueSize: Int = 64, 162 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 163 StoreQueueForwardWithMask: Boolean = true, 164 VlsQueueSize: Int = 8, 165 RobSize: Int = 160, 166 RabSize: Int = 256, 167 VTypeBufferSize: Int = 64, // used to reorder vtype 168 IssueQueueSize: Int = 24, 169 IssueQueueCompEntrySize: Int = 16, 170 dpParams: DispatchParameters = DispatchParameters( 171 IntDqSize = 16, 172 FpDqSize = 16, 173 LsDqSize = 18, 174 IntDqDeqWidth = 8, 175 FpDqDeqWidth = 6, 176 LsDqDeqWidth = 6, 177 ), 178 intPreg: PregParams = IntPregParams( 179 numEntries = 224, 180 numRead = None, 181 numWrite = None, 182 ), 183 vfPreg: VfPregParams = VfPregParams( 184 numEntries = 192, 185 numRead = None, 186 numWrite = None, 187 ), 188 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 189 LoadPipelineWidth: Int = 3, 190 StorePipelineWidth: Int = 2, 191 VecLoadPipelineWidth: Int = 2, 192 VecStorePipelineWidth: Int = 2, 193 VecMemSrcInWidth: Int = 2, 194 VecMemInstWbWidth: Int = 1, 195 VecMemDispatchWidth: Int = 1, 196 StoreBufferSize: Int = 16, 197 StoreBufferThreshold: Int = 7, 198 EnsbufferWidth: Int = 2, 199 LoadDependencyWidth: Int = 2, 200 // ============ VLSU ============ 201 UsQueueSize: Int = 8, 202 VlFlowSize: Int = 32, 203 VlUopSize: Int = 32, 204 VsFlowL1Size: Int = 128, 205 VsFlowL2Size: Int = 32, 206 VsUopSize: Int = 32, 207 // ============================== 208 UncacheBufferSize: Int = 4, 209 EnableLoadToLoadForward: Boolean = false, 210 EnableFastForward: Boolean = true, 211 EnableLdVioCheckAfterReset: Boolean = true, 212 EnableSoftPrefetchAfterReset: Boolean = true, 213 EnableCacheErrorAfterReset: Boolean = true, 214 EnableAccurateLoadError: Boolean = true, 215 EnableUncacheWriteOutstanding: Boolean = false, 216 EnableStorePrefetchAtIssue: Boolean = false, 217 EnableStorePrefetchAtCommit: Boolean = false, 218 EnableAtCommitMissTrigger: Boolean = true, 219 EnableStorePrefetchSMS: Boolean = false, 220 EnableStorePrefetchSPB: Boolean = false, 221 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 222 MMUVmidLen: Int = 14, 223 ReSelectLen: Int = 7, // load replay queue replay select counter len 224 iwpuParameters: WPUParameters = WPUParameters( 225 enWPU = false, 226 algoName = "mmru", 227 isICache = true, 228 ), 229 dwpuParameters: WPUParameters = WPUParameters( 230 enWPU = false, 231 algoName = "mmru", 232 enCfPred = false, 233 isICache = false, 234 ), 235 itlbParameters: TLBParameters = TLBParameters( 236 name = "itlb", 237 fetchi = true, 238 useDmode = false, 239 NWays = 48, 240 ), 241 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 242 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 243 ldtlbParameters: TLBParameters = TLBParameters( 244 name = "ldtlb", 245 NWays = 48, 246 outReplace = false, 247 partialStaticPMP = true, 248 outsideRecvFlush = true, 249 saveLevel = true 250 ), 251 sttlbParameters: TLBParameters = TLBParameters( 252 name = "sttlb", 253 NWays = 48, 254 outReplace = false, 255 partialStaticPMP = true, 256 outsideRecvFlush = true, 257 saveLevel = true 258 ), 259 hytlbParameters: TLBParameters = TLBParameters( 260 name = "hytlb", 261 NWays = 48, 262 outReplace = false, 263 partialStaticPMP = true, 264 outsideRecvFlush = true, 265 saveLevel = true 266 ), 267 pftlbParameters: TLBParameters = TLBParameters( 268 name = "pftlb", 269 NWays = 48, 270 outReplace = false, 271 partialStaticPMP = true, 272 outsideRecvFlush = true, 273 saveLevel = true 274 ), 275 l2ToL1tlbParameters: TLBParameters = TLBParameters( 276 name = "l2tlb", 277 NWays = 48, 278 outReplace = false, 279 partialStaticPMP = true, 280 outsideRecvFlush = true, 281 saveLevel = true 282 ), 283 refillBothTlb: Boolean = false, 284 btlbParameters: TLBParameters = TLBParameters( 285 name = "btlb", 286 NWays = 48, 287 ), 288 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 289 NumPerfCounters: Int = 16, 290 icacheParameters: ICacheParameters = ICacheParameters( 291 tagECC = Some("parity"), 292 dataECC = Some("parity"), 293 replacer = Some("setplru"), 294 nMissEntries = 2, 295 nProbeEntries = 2, 296 nPrefetchEntries = 12, 297 nPrefBufferEntries = 32, 298 ), 299 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 300 tagECC = Some("secded"), 301 dataECC = Some("secded"), 302 replacer = Some("setplru"), 303 nMissEntries = 16, 304 nProbeEntries = 8, 305 nReleaseEntries = 18, 306 nMaxPrefetchEntry = 6, 307 )), 308 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 309 name = "l2", 310 ways = 8, 311 sets = 1024, // default 512KB L2 312 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 313 )), 314 L2NBanks: Int = 1, 315 usePTWRepeater: Boolean = false, 316 softTLB: Boolean = false, // dpi-c l1tlb debug only 317 softPTW: Boolean = false, // dpi-c l2tlb debug only 318 softPTWDelay: Int = 1 319){ 320 def vlWidth = log2Up(VLEN) + 1 321 322 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 323 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 324 325 val intSchdParams = { 326 implicit val schdType: SchedulerType = IntScheduler() 327 SchdBlockParams(Seq( 328 IssueBlockParams(Seq( 329 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 330 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(7, 1))), true, 2), 331 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 332 IssueBlockParams(Seq( 333 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 334 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 2, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(5, 1))), true, 2), 335 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 336 IssueBlockParams(Seq( 337 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 338 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 3, 1), VfWB(5, 1)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(3, 1)))), 339 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 340 IssueBlockParams(Seq( 341 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 342 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(1, 1)))), 343 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 344 ), 345 numPregs = intPreg.numEntries, 346 numDeqOutside = 0, 347 schdType = schdType, 348 rfDataWidth = intPreg.dataCfg.dataWidth, 349 numUopIn = dpParams.IntDqDeqWidth, 350 ) 351 } 352 val vfSchdParams = { 353 implicit val schdType: SchedulerType = VfScheduler() 354 SchdBlockParams(Seq( 355 IssueBlockParams(Seq( 356 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 357 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 5, 0), IntWB(port = 2, 2)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 358 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 359 IssueBlockParams(Seq( 360 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg, F2vCfg), Seq(VfWB(port = 6, 0)), Seq(Seq(VfRD(7, 1)), Seq(VfRD(8, 1)), Seq(VfRD(9, 1)), Seq(VfRD(5, 1)), Seq(VfRD(6, 1)))), 361 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 7, 0), IntWB(port = 3, 2)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)))), 362 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 363 IssueBlockParams(Seq( 364 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 7, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(0, 2)), Seq(VfRD(1, 2)), Seq(VfRD(2, 2)))), 365 ExeUnitParams("VFEX5", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 6, 1)), Seq(Seq(VfRD(8, 2)), Seq(VfRD(9, 2)), Seq(VfRD(5, 2)), Seq(VfRD(6, 2)), Seq(VfRD(7, 2)))), 366 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 367 ), 368 numPregs = vfPreg.numEntries, 369 numDeqOutside = 0, 370 schdType = schdType, 371 rfDataWidth = vfPreg.dataCfg.dataWidth, 372 numUopIn = dpParams.FpDqDeqWidth, 373 ) 374 } 375 376 val memSchdParams = { 377 implicit val schdType: SchedulerType = MemScheduler() 378 val rfDataWidth = 64 379 380 SchdBlockParams(Seq( 381 IssueBlockParams(Seq( 382 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(8, 1)))), 383 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 384 IssueBlockParams(Seq( 385 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(9, 1)))), 386 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 387 IssueBlockParams(Seq( 388 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), VfWB(0, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 389 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 390 IssueBlockParams(Seq( 391 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(1, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 392 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 393 IssueBlockParams(Seq( 394 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(2, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 395 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 396 IssueBlockParams(Seq( 397 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(VfRD(12, 0)), Seq(VfRD(13, 0)), Seq(VfRD(14, 0)))), 398 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 399 IssueBlockParams(Seq( 400 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(10, 1), VfRD(12, Int.MaxValue)))), 401 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 402 IssueBlockParams(Seq( 403 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(11, 1), VfRD(13, Int.MaxValue)))), 404 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 405 ), 406 numPregs = intPreg.numEntries max vfPreg.numEntries, 407 numDeqOutside = 0, 408 schdType = schdType, 409 rfDataWidth = rfDataWidth, 410 numUopIn = dpParams.LsDqDeqWidth, 411 ) 412 } 413 414 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 415 416 def iqWakeUpParams = { 417 Seq( 418 WakeUpConfig( 419 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 420 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 421 ), 422 WakeUpConfig( 423 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "LDU0", "LDU1", "LDU2") -> 424 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "VFEX4", "VFEX5") 425 ), 426 WakeUpConfig( 427 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 428 Seq("STD0", "STD1") 429 ), 430 ).flatten 431 } 432 433 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 434 435 val backendParams: BackendParams = backend.BackendParams( 436 Map( 437 IntScheduler() -> intSchdParams, 438 VfScheduler() -> vfSchdParams, 439 MemScheduler() -> memSchdParams, 440 ), 441 Seq( 442 intPreg, 443 vfPreg, 444 fakeIntPreg 445 ), 446 iqWakeUpParams, 447 ) 448} 449 450case object DebugOptionsKey extends Field[DebugOptions] 451 452case class DebugOptions 453( 454 FPGAPlatform: Boolean = false, 455 EnableDifftest: Boolean = false, 456 AlwaysBasicDiff: Boolean = true, 457 EnableDebug: Boolean = false, 458 EnablePerfDebug: Boolean = true, 459 UseDRAMSim: Boolean = false, 460 EnableConstantin: Boolean = false, 461 EnableChiselDB: Boolean = false, 462 AlwaysBasicDB: Boolean = true, 463 EnableTopDown: Boolean = false, 464 EnableRollingDB: Boolean = false 465) 466 467trait HasXSParameter { 468 469 implicit val p: Parameters 470 471 def PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 472 473 def coreParams = p(XSCoreParamsKey) 474 def env = p(DebugOptionsKey) 475 476 def XLEN = coreParams.XLEN 477 def VLEN = coreParams.VLEN 478 def ELEN = coreParams.ELEN 479 def HSXLEN = coreParams.HSXLEN 480 val minFLen = 32 481 val fLen = 64 482 def hartIdLen = p(MaxHartIdBits) 483 val xLen = XLEN 484 485 def HasMExtension = coreParams.HasMExtension 486 def HasCExtension = coreParams.HasCExtension 487 def HasHExtension = coreParams.HasHExtension 488 def HasDiv = coreParams.HasDiv 489 def HasIcache = coreParams.HasICache 490 def HasDcache = coreParams.HasDCache 491 def AddrBits = coreParams.AddrBits // AddrBits is used in some cases 492 def GPAddrBits = coreParams.GPAddrBits 493 def VAddrBits = { 494 if(HasHExtension){ 495 coreParams.GPAddrBits 496 }else{ 497 coreParams.VAddrBits 498 } 499 } // VAddrBits is Virtual Memory addr bits 500 501 def AsidLength = coreParams.AsidLength 502 def VmidLength = coreParams.VmidLength 503 def ReSelectLen = coreParams.ReSelectLen 504 def AddrBytes = AddrBits / 8 // unused 505 def DataBits = XLEN 506 def DataBytes = DataBits / 8 507 def VDataBytes = VLEN / 8 508 def HasFPU = coreParams.HasFPU 509 def HasVPU = coreParams.HasVPU 510 def HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 511 def FetchWidth = coreParams.FetchWidth 512 def PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 513 def EnableBPU = coreParams.EnableBPU 514 def EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 515 def EnableRAS = coreParams.EnableRAS 516 def EnableLB = coreParams.EnableLB 517 def EnableLoop = coreParams.EnableLoop 518 def EnableSC = coreParams.EnableSC 519 def EnbaleTlbDebug = coreParams.EnbaleTlbDebug 520 def HistoryLength = coreParams.HistoryLength 521 def EnableGHistDiff = coreParams.EnableGHistDiff 522 def EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 523 def EnableClockGate = coreParams.EnableClockGate 524 def UbtbGHRLength = coreParams.UbtbGHRLength 525 def UbtbSize = coreParams.UbtbSize 526 def EnableFauFTB = coreParams.EnableFauFTB 527 def FtbSize = coreParams.FtbSize 528 def FtbWays = coreParams.FtbWays 529 def RasSize = coreParams.RasSize 530 def RasSpecSize = coreParams.RasSpecSize 531 def RasCtrSize = coreParams.RasCtrSize 532 533 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 534 coreParams.branchPredictor(resp_in, p) 535 } 536 def numBr = coreParams.numBr 537 def TageTableInfos = coreParams.TageTableInfos 538 def TageBanks = coreParams.numBr 539 def SCNRows = coreParams.SCNRows 540 def SCCtrBits = coreParams.SCCtrBits 541 def SCHistLens = coreParams.SCHistLens 542 def SCNTables = coreParams.SCNTables 543 544 def SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 545 case ((n, cb), h) => (n, cb, h) 546 } 547 def ITTageTableInfos = coreParams.ITTageTableInfos 548 type FoldedHistoryInfo = Tuple2[Int, Int] 549 def foldedGHistInfos = 550 (TageTableInfos.map{ case (nRows, h, t) => 551 if (h > 0) 552 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 553 else 554 Set[FoldedHistoryInfo]() 555 }.reduce(_++_).toSet ++ 556 SCTableInfos.map{ case (nRows, _, h) => 557 if (h > 0) 558 Set((h, min(log2Ceil(nRows/TageBanks), h))) 559 else 560 Set[FoldedHistoryInfo]() 561 }.reduce(_++_).toSet ++ 562 ITTageTableInfos.map{ case (nRows, h, t) => 563 if (h > 0) 564 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 565 else 566 Set[FoldedHistoryInfo]() 567 }.reduce(_++_) ++ 568 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 569 ).toList 570 571 572 573 def CacheLineSize = coreParams.CacheLineSize 574 def CacheLineHalfWord = CacheLineSize / 16 575 def ExtHistoryLength = HistoryLength + 64 576 def ICacheECCForceError = coreParams.ICacheECCForceError 577 def IBufSize = coreParams.IBufSize 578 def IBufNBank = coreParams.IBufNBank 579 def backendParams: BackendParams = coreParams.backendParams 580 def DecodeWidth = coreParams.DecodeWidth 581 def RenameWidth = coreParams.RenameWidth 582 def CommitWidth = coreParams.CommitWidth 583 def RobCommitWidth = coreParams.RobCommitWidth 584 def RabCommitWidth = coreParams.RabCommitWidth 585 def MaxUopSize = coreParams.MaxUopSize 586 def EnableRenameSnapshot = coreParams.EnableRenameSnapshot 587 def RenameSnapshotNum = coreParams.RenameSnapshotNum 588 def FtqSize = coreParams.FtqSize 589 def EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 590 def IntLogicRegs = coreParams.IntLogicRegs 591 def FpLogicRegs = coreParams.FpLogicRegs 592 def VecLogicRegs = coreParams.VecLogicRegs 593 def VCONFIG_IDX = coreParams.VCONFIG_IDX 594 def IntPhyRegs = coreParams.intPreg.numEntries 595 def VfPhyRegs = coreParams.vfPreg.numEntries 596 def MaxPhyPregs = IntPhyRegs max VfPhyRegs 597 def PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 598 def RobSize = coreParams.RobSize 599 def RabSize = coreParams.RabSize 600 def VTypeBufferSize = coreParams.VTypeBufferSize 601 def IntRefCounterWidth = log2Ceil(RobSize) 602 def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 603 def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 604 def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 605 def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 606 def LoadQueueRARSize = coreParams.LoadQueueRARSize 607 def LoadQueueRAWSize = coreParams.LoadQueueRAWSize 608 def RollbackGroupSize = coreParams.RollbackGroupSize 609 def LoadQueueReplaySize = coreParams.LoadQueueReplaySize 610 def LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 611 def LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 612 def StoreQueueSize = coreParams.StoreQueueSize 613 def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 614 def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 615 def VlsQueueSize = coreParams.VlsQueueSize 616 def dpParams = coreParams.dpParams 617 618 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 619 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 620 621 def NumRedirect = backendParams.numRedirect 622 def BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 623 def FtqRedirectAheadNum = NumRedirect 624 def LoadPipelineWidth = coreParams.LoadPipelineWidth 625 def StorePipelineWidth = coreParams.StorePipelineWidth 626 def VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 627 def VecStorePipelineWidth = coreParams.VecStorePipelineWidth 628 def VecMemSrcInWidth = coreParams.VecMemSrcInWidth 629 def VecMemInstWbWidth = coreParams.VecMemInstWbWidth 630 def VecMemDispatchWidth = coreParams.VecMemDispatchWidth 631 def StoreBufferSize = coreParams.StoreBufferSize 632 def StoreBufferThreshold = coreParams.StoreBufferThreshold 633 def EnsbufferWidth = coreParams.EnsbufferWidth 634 def LoadDependencyWidth = coreParams.LoadDependencyWidth 635 def UsQueueSize = coreParams.UsQueueSize 636 def VlFlowSize = coreParams.VlFlowSize 637 def VlUopSize = coreParams.VlUopSize 638 def VsFlowL1Size = coreParams.VsFlowL1Size 639 def VsFlowL2Size = coreParams.VsFlowL2Size 640 def VsUopSize = coreParams.VsUopSize 641 def UncacheBufferSize = coreParams.UncacheBufferSize 642 def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 643 def EnableFastForward = coreParams.EnableFastForward 644 def EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 645 def EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 646 def EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 647 def EnableAccurateLoadError = coreParams.EnableAccurateLoadError 648 def EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 649 def EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 650 def EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 651 def EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 652 def EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 653 def EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 654 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 655 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 656 def Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 657 def asidLen = coreParams.MMUAsidLen 658 def vmidLen = coreParams.MMUVmidLen 659 def BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 660 def refillBothTlb = coreParams.refillBothTlb 661 def iwpuParam = coreParams.iwpuParameters 662 def dwpuParam = coreParams.dwpuParameters 663 def itlbParams = coreParams.itlbParameters 664 def ldtlbParams = coreParams.ldtlbParameters 665 def sttlbParams = coreParams.sttlbParameters 666 def hytlbParams = coreParams.hytlbParameters 667 def pftlbParams = coreParams.pftlbParameters 668 def l2ToL1Params = coreParams.l2ToL1tlbParameters 669 def btlbParams = coreParams.btlbParameters 670 def l2tlbParams = coreParams.l2tlbParameters 671 def NumPerfCounters = coreParams.NumPerfCounters 672 673 def instBytes = if (HasCExtension) 2 else 4 674 def instOffsetBits = log2Ceil(instBytes) 675 676 def icacheParameters = coreParams.icacheParameters 677 def dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 678 679 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 680 // for constrained LR/SC loop 681 def LRSCCycles = 64 682 // for lr storm 683 def LRSCBackOff = 8 684 685 // cache hierarchy configurations 686 def l1BusDataWidth = 256 687 688 // load violation predict 689 def ResetTimeMax2Pow = 20 //1078576 690 def ResetTimeMin2Pow = 10 //1024 691 // wait table parameters 692 def WaitTableSize = 1024 693 def MemPredPCWidth = log2Up(WaitTableSize) 694 def LWTUse2BitCounter = true 695 // store set parameters 696 def SSITSize = WaitTableSize 697 def LFSTSize = 32 698 def SSIDWidth = log2Up(LFSTSize) 699 def LFSTWidth = 4 700 def StoreSetEnable = true // LWT will be disabled if SS is enabled 701 def LFSTEnable = true 702 703 def PCntIncrStep: Int = 6 704 def numPCntHc: Int = 25 705 def numPCntPtw: Int = 19 706 707 def numCSRPCntFrontend = 8 708 def numCSRPCntCtrl = 8 709 def numCSRPCntLsu = 8 710 def numCSRPCntHc = 5 711 def printEventCoding = true 712 713 // Parameters for Sdtrig extension 714 protected def TriggerNum = 4 715 protected def TriggerChainMaxLength = 2 716} 717