1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams, FakeIntPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import freechips.rocketchip.tile.MaxHartIdBits 42import system.SoCParamsKey 43import huancun._ 44import huancun.debug._ 45import xiangshan.cache.wpu.WPUParameters 46import coupledL2._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.min 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBits: Int = 39, 72 GPAddrBits: Int = 41, 73 HasFPU: Boolean = true, 74 HasVPU: Boolean = true, 75 HasCustomCSRCacheOp: Boolean = true, 76 FetchWidth: Int = 8, 77 AsidLength: Int = 16, 78 VmidLength: Int = 14, 79 EnableBPU: Boolean = true, 80 EnableBPD: Boolean = true, 81 EnableRAS: Boolean = true, 82 EnableLB: Boolean = false, 83 EnableLoop: Boolean = true, 84 EnableSC: Boolean = true, 85 EnbaleTlbDebug: Boolean = false, 86 EnableClockGate: Boolean = true, 87 EnableJal: Boolean = false, 88 EnableFauFTB: Boolean = true, 89 UbtbGHRLength: Int = 4, 90 // HistoryLength: Int = 512, 91 EnableGHistDiff: Boolean = true, 92 EnableCommitGHistDiff: Boolean = true, 93 UbtbSize: Int = 256, 94 FtbSize: Int = 2048, 95 RasSize: Int = 16, 96 RasSpecSize: Int = 32, 97 RasCtrSize: Int = 3, 98 CacheLineSize: Int = 512, 99 FtbWays: Int = 4, 100 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 101 // Sets Hist Tag 102 // Seq(( 2048, 2, 8), 103 // ( 2048, 9, 8), 104 // ( 2048, 13, 8), 105 // ( 2048, 20, 8), 106 // ( 2048, 26, 8), 107 // ( 2048, 44, 8), 108 // ( 2048, 73, 8), 109 // ( 2048, 256, 8)), 110 Seq(( 4096, 8, 8), 111 ( 4096, 13, 8), 112 ( 4096, 32, 8), 113 ( 4096, 119, 8)), 114 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 115 // Sets Hist Tag 116 Seq(( 256, 4, 9), 117 ( 256, 8, 9), 118 ( 512, 13, 9), 119 ( 512, 16, 9), 120 ( 512, 32, 9)), 121 SCNRows: Int = 512, 122 SCNTables: Int = 4, 123 SCCtrBits: Int = 6, 124 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 125 numBr: Int = 2, 126 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 127 ((resp_in: BranchPredictionResp, p: Parameters) => { 128 val ftb = Module(new FTB()(p)) 129 val ubtb =Module(new FauFTB()(p)) 130 // val bim = Module(new BIM()(p)) 131 val tage = Module(new Tage_SC()(p)) 132 val ras = Module(new RAS()(p)) 133 val ittage = Module(new ITTage()(p)) 134 val preds = Seq(ubtb, tage, ftb, ittage, ras) 135 preds.map(_.io := DontCare) 136 137 // ubtb.io.resp_in(0) := resp_in 138 // bim.io.resp_in(0) := ubtb.io.resp 139 // btb.io.resp_in(0) := bim.io.resp 140 // tage.io.resp_in(0) := btb.io.resp 141 // loop.io.resp_in(0) := tage.io.resp 142 ubtb.io.in.bits.resp_in(0) := resp_in 143 tage.io.in.bits.resp_in(0) := ubtb.io.out 144 ftb.io.in.bits.resp_in(0) := tage.io.out 145 ittage.io.in.bits.resp_in(0) := ftb.io.out 146 ras.io.in.bits.resp_in(0) := ittage.io.out 147 148 (preds, ras.io.out) 149 }), 150 ICacheECCForceError: Boolean = false, 151 IBufSize: Int = 48, 152 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 153 DecodeWidth: Int = 6, 154 RenameWidth: Int = 6, 155 CommitWidth: Int = 8, 156 RobCommitWidth: Int = 8, 157 RabCommitWidth: Int = 6, 158 MaxUopSize: Int = 65, 159 EnableRenameSnapshot: Boolean = true, 160 RenameSnapshotNum: Int = 4, 161 FtqSize: Int = 64, 162 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 163 IntLogicRegs: Int = 32, 164 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 165 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 166 VCONFIG_IDX: Int = 32, 167 NRPhyRegs: Int = 192, 168 VirtualLoadQueueSize: Int = 72, 169 LoadQueueRARSize: Int = 72, 170 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 171 RollbackGroupSize: Int = 8, 172 LoadQueueReplaySize: Int = 72, 173 LoadUncacheBufferSize: Int = 20, 174 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 175 StoreQueueSize: Int = 64, 176 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 177 StoreQueueForwardWithMask: Boolean = true, 178 VlsQueueSize: Int = 8, 179 RobSize: Int = 160, 180 RabSize: Int = 256, 181 VTypeBufferSize: Int = 64, // used to reorder vtype 182 IssueQueueSize: Int = 24, 183 IssueQueueCompEntrySize: Int = 16, 184 dpParams: DispatchParameters = DispatchParameters( 185 IntDqSize = 16, 186 FpDqSize = 16, 187 LsDqSize = 18, 188 IntDqDeqWidth = 8, 189 FpDqDeqWidth = 6, 190 LsDqDeqWidth = 6, 191 ), 192 intPreg: PregParams = IntPregParams( 193 numEntries = 224, 194 numRead = None, 195 numWrite = None, 196 ), 197 vfPreg: VfPregParams = VfPregParams( 198 numEntries = 192, 199 numRead = None, 200 numWrite = None, 201 ), 202 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 203 LoadPipelineWidth: Int = 3, 204 StorePipelineWidth: Int = 2, 205 VecLoadPipelineWidth: Int = 2, 206 VecStorePipelineWidth: Int = 2, 207 VecMemSrcInWidth: Int = 2, 208 VecMemInstWbWidth: Int = 1, 209 VecMemDispatchWidth: Int = 1, 210 StoreBufferSize: Int = 16, 211 StoreBufferThreshold: Int = 7, 212 EnsbufferWidth: Int = 2, 213 LoadDependencyWidth: Int = 2, 214 // ============ VLSU ============ 215 UsQueueSize: Int = 8, 216 VlFlowSize: Int = 32, 217 VlUopSize: Int = 32, 218 VsFlowL1Size: Int = 128, 219 VsFlowL2Size: Int = 32, 220 VsUopSize: Int = 32, 221 // ============================== 222 UncacheBufferSize: Int = 4, 223 EnableLoadToLoadForward: Boolean = false, 224 EnableFastForward: Boolean = true, 225 EnableLdVioCheckAfterReset: Boolean = true, 226 EnableSoftPrefetchAfterReset: Boolean = true, 227 EnableCacheErrorAfterReset: Boolean = true, 228 EnableAccurateLoadError: Boolean = true, 229 EnableUncacheWriteOutstanding: Boolean = false, 230 EnableStorePrefetchAtIssue: Boolean = false, 231 EnableStorePrefetchAtCommit: Boolean = false, 232 EnableAtCommitMissTrigger: Boolean = true, 233 EnableStorePrefetchSMS: Boolean = false, 234 EnableStorePrefetchSPB: Boolean = false, 235 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 236 MMUVmidLen: Int = 14, 237 ReSelectLen: Int = 7, // load replay queue replay select counter len 238 iwpuParameters: WPUParameters = WPUParameters( 239 enWPU = false, 240 algoName = "mmru", 241 isICache = true, 242 ), 243 dwpuParameters: WPUParameters = WPUParameters( 244 enWPU = false, 245 algoName = "mmru", 246 enCfPred = false, 247 isICache = false, 248 ), 249 itlbParameters: TLBParameters = TLBParameters( 250 name = "itlb", 251 fetchi = true, 252 useDmode = false, 253 NWays = 48, 254 ), 255 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 256 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 257 ldtlbParameters: TLBParameters = TLBParameters( 258 name = "ldtlb", 259 NWays = 48, 260 outReplace = false, 261 partialStaticPMP = true, 262 outsideRecvFlush = true, 263 saveLevel = true 264 ), 265 sttlbParameters: TLBParameters = TLBParameters( 266 name = "sttlb", 267 NWays = 48, 268 outReplace = false, 269 partialStaticPMP = true, 270 outsideRecvFlush = true, 271 saveLevel = true 272 ), 273 hytlbParameters: TLBParameters = TLBParameters( 274 name = "hytlb", 275 NWays = 48, 276 outReplace = false, 277 partialStaticPMP = true, 278 outsideRecvFlush = true, 279 saveLevel = true 280 ), 281 pftlbParameters: TLBParameters = TLBParameters( 282 name = "pftlb", 283 NWays = 48, 284 outReplace = false, 285 partialStaticPMP = true, 286 outsideRecvFlush = true, 287 saveLevel = true 288 ), 289 refillBothTlb: Boolean = false, 290 btlbParameters: TLBParameters = TLBParameters( 291 name = "btlb", 292 NWays = 48, 293 ), 294 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 295 NumPerfCounters: Int = 16, 296 icacheParameters: ICacheParameters = ICacheParameters( 297 tagECC = Some("parity"), 298 dataECC = Some("parity"), 299 replacer = Some("setplru"), 300 nMissEntries = 2, 301 nProbeEntries = 2, 302 nPrefetchEntries = 12, 303 nPrefBufferEntries = 32, 304 ), 305 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 306 tagECC = Some("secded"), 307 dataECC = Some("secded"), 308 replacer = Some("setplru"), 309 nMissEntries = 16, 310 nProbeEntries = 8, 311 nReleaseEntries = 18, 312 nMaxPrefetchEntry = 6, 313 )), 314 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 315 name = "l2", 316 ways = 8, 317 sets = 1024, // default 512KB L2 318 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 319 )), 320 L2NBanks: Int = 1, 321 usePTWRepeater: Boolean = false, 322 softTLB: Boolean = false, // dpi-c l1tlb debug only 323 softPTW: Boolean = false, // dpi-c l2tlb debug only 324 softPTWDelay: Int = 1 325){ 326 def vlWidth = log2Up(VLEN) + 1 327 328 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 329 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 330 331 val intSchdParams = { 332 implicit val schdType: SchedulerType = IntScheduler() 333 SchdBlockParams(Seq( 334 IssueBlockParams(Seq( 335 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 336 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(7, 1))), true, 2), 337 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 338 IssueBlockParams(Seq( 339 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 340 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 2, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(5, 1))), true, 2), 341 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 342 IssueBlockParams(Seq( 343 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 344 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 3, 1), VfWB(5, 1)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(3, 1)))), 345 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 346 IssueBlockParams(Seq( 347 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 348 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(1, 1)))), 349 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 350 ), 351 numPregs = intPreg.numEntries, 352 numDeqOutside = 0, 353 schdType = schdType, 354 rfDataWidth = intPreg.dataCfg.dataWidth, 355 numUopIn = dpParams.IntDqDeqWidth, 356 ) 357 } 358 val vfSchdParams = { 359 implicit val schdType: SchedulerType = VfScheduler() 360 SchdBlockParams(Seq( 361 IssueBlockParams(Seq( 362 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 363 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 5, 0), IntWB(port = 2, 2)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 364 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 365 IssueBlockParams(Seq( 366 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg, F2vCfg), Seq(VfWB(port = 6, 0)), Seq(Seq(VfRD(7, 1)), Seq(VfRD(8, 1)), Seq(VfRD(9, 1)), Seq(VfRD(5, 1)), Seq(VfRD(6, 1)))), 367 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 7, 0), IntWB(port = 3, 2)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)))), 368 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 369 IssueBlockParams(Seq( 370 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 7, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(0, 2)), Seq(VfRD(1, 2)), Seq(VfRD(2, 2)))), 371 ExeUnitParams("VFEX5", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 6, 1)), Seq(Seq(VfRD(8, 2)), Seq(VfRD(9, 2)), Seq(VfRD(5, 2)), Seq(VfRD(6, 2)), Seq(VfRD(7, 2)))), 372 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 373 ), 374 numPregs = vfPreg.numEntries, 375 numDeqOutside = 0, 376 schdType = schdType, 377 rfDataWidth = vfPreg.dataCfg.dataWidth, 378 numUopIn = dpParams.FpDqDeqWidth, 379 ) 380 } 381 382 val memSchdParams = { 383 implicit val schdType: SchedulerType = MemScheduler() 384 val rfDataWidth = 64 385 386 SchdBlockParams(Seq( 387 IssueBlockParams(Seq( 388 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(8, 1)))), 389 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 390 IssueBlockParams(Seq( 391 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(9, 1)))), 392 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 393 IssueBlockParams(Seq( 394 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), VfWB(0, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 395 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 396 IssueBlockParams(Seq( 397 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(1, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 398 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 399 IssueBlockParams(Seq( 400 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(2, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 401 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 402 IssueBlockParams(Seq( 403 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(VfRD(12, 0)), Seq(VfRD(13, 0)), Seq(VfRD(14, 0)))), 404 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 405 IssueBlockParams(Seq( 406 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(10, 1), VfRD(12, Int.MaxValue)))), 407 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 408 IssueBlockParams(Seq( 409 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(11, 1), VfRD(13, Int.MaxValue)))), 410 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 411 ), 412 numPregs = intPreg.numEntries max vfPreg.numEntries, 413 numDeqOutside = 0, 414 schdType = schdType, 415 rfDataWidth = rfDataWidth, 416 numUopIn = dpParams.LsDqDeqWidth, 417 ) 418 } 419 420 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 421 422 def iqWakeUpParams = { 423 Seq( 424 WakeUpConfig( 425 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 426 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 427 ), 428 WakeUpConfig( 429 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "LDU0", "LDU1", "LDU2") -> 430 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "VFEX4", "VFEX5") 431 ), 432 WakeUpConfig( 433 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 434 Seq("STD0", "STD1") 435 ), 436 ).flatten 437 } 438 439 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 440 441 val backendParams: BackendParams = backend.BackendParams( 442 Map( 443 IntScheduler() -> intSchdParams, 444 VfScheduler() -> vfSchdParams, 445 MemScheduler() -> memSchdParams, 446 ), 447 Seq( 448 intPreg, 449 vfPreg, 450 fakeIntPreg 451 ), 452 iqWakeUpParams, 453 ) 454} 455 456case object DebugOptionsKey extends Field[DebugOptions] 457 458case class DebugOptions 459( 460 FPGAPlatform: Boolean = false, 461 EnableDifftest: Boolean = false, 462 AlwaysBasicDiff: Boolean = true, 463 EnableDebug: Boolean = false, 464 EnablePerfDebug: Boolean = true, 465 UseDRAMSim: Boolean = false, 466 EnableConstantin: Boolean = false, 467 EnableChiselDB: Boolean = false, 468 AlwaysBasicDB: Boolean = true, 469 EnableTopDown: Boolean = false, 470 EnableRollingDB: Boolean = false 471) 472 473trait HasXSParameter { 474 475 implicit val p: Parameters 476 477 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 478 479 val coreParams = p(XSCoreParamsKey) 480 val env = p(DebugOptionsKey) 481 482 val XLEN = coreParams.XLEN 483 val VLEN = coreParams.VLEN 484 val ELEN = coreParams.ELEN 485 val HSXLEN = coreParams.HSXLEN 486 val minFLen = 32 487 val fLen = 64 488 val hartIdLen = p(MaxHartIdBits) 489 def xLen = XLEN 490 491 val HasMExtension = coreParams.HasMExtension 492 val HasCExtension = coreParams.HasCExtension 493 val HasHExtension = coreParams.HasHExtension 494 val HasDiv = coreParams.HasDiv 495 val HasIcache = coreParams.HasICache 496 val HasDcache = coreParams.HasDCache 497 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 498 val GPAddrBits = coreParams.GPAddrBits 499 val VAddrBits = { 500 if(HasHExtension){ 501 coreParams.GPAddrBits 502 }else{ 503 coreParams.VAddrBits 504 } 505 } // VAddrBits is Virtual Memory addr bits 506 507 val AsidLength = coreParams.AsidLength 508 val VmidLength = coreParams.VmidLength 509 val ReSelectLen = coreParams.ReSelectLen 510 val AddrBytes = AddrBits / 8 // unused 511 val DataBits = XLEN 512 val DataBytes = DataBits / 8 513 val VDataBytes = VLEN / 8 514 val HasFPU = coreParams.HasFPU 515 val HasVPU = coreParams.HasVPU 516 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 517 val FetchWidth = coreParams.FetchWidth 518 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 519 val EnableBPU = coreParams.EnableBPU 520 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 521 val EnableRAS = coreParams.EnableRAS 522 val EnableLB = coreParams.EnableLB 523 val EnableLoop = coreParams.EnableLoop 524 val EnableSC = coreParams.EnableSC 525 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 526 val HistoryLength = coreParams.HistoryLength 527 val EnableGHistDiff = coreParams.EnableGHistDiff 528 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 529 val EnableClockGate = coreParams.EnableClockGate 530 val UbtbGHRLength = coreParams.UbtbGHRLength 531 val UbtbSize = coreParams.UbtbSize 532 val EnableFauFTB = coreParams.EnableFauFTB 533 val FtbSize = coreParams.FtbSize 534 val FtbWays = coreParams.FtbWays 535 val RasSize = coreParams.RasSize 536 val RasSpecSize = coreParams.RasSpecSize 537 val RasCtrSize = coreParams.RasCtrSize 538 539 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 540 coreParams.branchPredictor(resp_in, p) 541 } 542 val numBr = coreParams.numBr 543 val TageTableInfos = coreParams.TageTableInfos 544 val TageBanks = coreParams.numBr 545 val SCNRows = coreParams.SCNRows 546 val SCCtrBits = coreParams.SCCtrBits 547 val SCHistLens = coreParams.SCHistLens 548 val SCNTables = coreParams.SCNTables 549 550 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 551 case ((n, cb), h) => (n, cb, h) 552 } 553 val ITTageTableInfos = coreParams.ITTageTableInfos 554 type FoldedHistoryInfo = Tuple2[Int, Int] 555 val foldedGHistInfos = 556 (TageTableInfos.map{ case (nRows, h, t) => 557 if (h > 0) 558 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 559 else 560 Set[FoldedHistoryInfo]() 561 }.reduce(_++_).toSet ++ 562 SCTableInfos.map{ case (nRows, _, h) => 563 if (h > 0) 564 Set((h, min(log2Ceil(nRows/TageBanks), h))) 565 else 566 Set[FoldedHistoryInfo]() 567 }.reduce(_++_).toSet ++ 568 ITTageTableInfos.map{ case (nRows, h, t) => 569 if (h > 0) 570 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 571 else 572 Set[FoldedHistoryInfo]() 573 }.reduce(_++_) ++ 574 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 575 ).toList 576 577 578 579 val CacheLineSize = coreParams.CacheLineSize 580 val CacheLineHalfWord = CacheLineSize / 16 581 val ExtHistoryLength = HistoryLength + 64 582 val ICacheECCForceError = coreParams.ICacheECCForceError 583 val IBufSize = coreParams.IBufSize 584 val IBufNBank = coreParams.IBufNBank 585 val backendParams: BackendParams = coreParams.backendParams 586 val DecodeWidth = coreParams.DecodeWidth 587 val RenameWidth = coreParams.RenameWidth 588 val CommitWidth = coreParams.CommitWidth 589 val RobCommitWidth = coreParams.RobCommitWidth 590 val RabCommitWidth = coreParams.RabCommitWidth 591 val MaxUopSize = coreParams.MaxUopSize 592 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 593 val RenameSnapshotNum = coreParams.RenameSnapshotNum 594 val FtqSize = coreParams.FtqSize 595 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 596 val IntLogicRegs = coreParams.IntLogicRegs 597 val FpLogicRegs = coreParams.FpLogicRegs 598 val VecLogicRegs = coreParams.VecLogicRegs 599 val VCONFIG_IDX = coreParams.VCONFIG_IDX 600 val IntPhyRegs = coreParams.intPreg.numEntries 601 val VfPhyRegs = coreParams.vfPreg.numEntries 602 val MaxPhyPregs = IntPhyRegs max VfPhyRegs 603 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 604 val RobSize = coreParams.RobSize 605 val RabSize = coreParams.RabSize 606 val VTypeBufferSize = coreParams.VTypeBufferSize 607 val IntRefCounterWidth = log2Ceil(RobSize) 608 val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 609 val LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 610 val LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 611 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 612 val LoadQueueRARSize = coreParams.LoadQueueRARSize 613 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 614 val RollbackGroupSize = coreParams.RollbackGroupSize 615 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 616 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 617 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 618 val StoreQueueSize = coreParams.StoreQueueSize 619 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 620 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 621 val VlsQueueSize = coreParams.VlsQueueSize 622 val dpParams = coreParams.dpParams 623 624 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 625 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 626 627 val NumRedirect = backendParams.numRedirect 628 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 629 val FtqRedirectAheadNum = NumRedirect 630 val LoadPipelineWidth = coreParams.LoadPipelineWidth 631 val StorePipelineWidth = coreParams.StorePipelineWidth 632 val VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 633 val VecStorePipelineWidth = coreParams.VecStorePipelineWidth 634 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 635 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 636 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 637 val StoreBufferSize = coreParams.StoreBufferSize 638 val StoreBufferThreshold = coreParams.StoreBufferThreshold 639 val EnsbufferWidth = coreParams.EnsbufferWidth 640 val LoadDependencyWidth = coreParams.LoadDependencyWidth 641 val UsQueueSize = coreParams.UsQueueSize 642 val VlFlowSize = coreParams.VlFlowSize 643 val VlUopSize = coreParams.VlUopSize 644 val VsFlowL1Size = coreParams.VsFlowL1Size 645 val VsFlowL2Size = coreParams.VsFlowL2Size 646 val VsUopSize = coreParams.VsUopSize 647 val UncacheBufferSize = coreParams.UncacheBufferSize 648 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 649 val EnableFastForward = coreParams.EnableFastForward 650 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 651 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 652 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 653 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 654 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 655 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 656 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 657 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 658 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 659 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 660 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 661 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 662 val Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 663 val asidLen = coreParams.MMUAsidLen 664 val vmidLen = coreParams.MMUVmidLen 665 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 666 val refillBothTlb = coreParams.refillBothTlb 667 val iwpuParam = coreParams.iwpuParameters 668 val dwpuParam = coreParams.dwpuParameters 669 val itlbParams = coreParams.itlbParameters 670 val ldtlbParams = coreParams.ldtlbParameters 671 val sttlbParams = coreParams.sttlbParameters 672 val hytlbParams = coreParams.hytlbParameters 673 val pftlbParams = coreParams.pftlbParameters 674 val btlbParams = coreParams.btlbParameters 675 val l2tlbParams = coreParams.l2tlbParameters 676 val NumPerfCounters = coreParams.NumPerfCounters 677 678 val instBytes = if (HasCExtension) 2 else 4 679 val instOffsetBits = log2Ceil(instBytes) 680 681 val icacheParameters = coreParams.icacheParameters 682 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 683 684 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 685 // for constrained LR/SC loop 686 val LRSCCycles = 64 687 // for lr storm 688 val LRSCBackOff = 8 689 690 // cache hierarchy configurations 691 val l1BusDataWidth = 256 692 693 // load violation predict 694 val ResetTimeMax2Pow = 20 //1078576 695 val ResetTimeMin2Pow = 10 //1024 696 // wait table parameters 697 val WaitTableSize = 1024 698 val MemPredPCWidth = log2Up(WaitTableSize) 699 val LWTUse2BitCounter = true 700 // store set parameters 701 val SSITSize = WaitTableSize 702 val LFSTSize = 32 703 val SSIDWidth = log2Up(LFSTSize) 704 val LFSTWidth = 4 705 val StoreSetEnable = true // LWT will be disabled if SS is enabled 706 val LFSTEnable = true 707 708 val PCntIncrStep: Int = 6 709 val numPCntHc: Int = 25 710 val numPCntPtw: Int = 19 711 712 val numCSRPCntFrontend = 8 713 val numCSRPCntCtrl = 8 714 val numCSRPCntLsu = 8 715 val numCSRPCntHc = 5 716 val printEventCoding = true 717 718 // Parameters for Sdtrig extension 719 protected val TriggerNum = 4 720 protected val TriggerChainMaxLength = 2 721} 722