1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams, FakeIntPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import freechips.rocketchip.tile.MaxHartIdBits 42import system.SoCParamsKey 43import huancun._ 44import huancun.debug._ 45import xiangshan.cache.wpu.WPUParameters 46import coupledL2._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.min 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBits: Int = 39, 72 GPAddrBits: Int = 41, 73 HasFPU: Boolean = true, 74 HasVPU: Boolean = true, 75 HasCustomCSRCacheOp: Boolean = true, 76 FetchWidth: Int = 8, 77 AsidLength: Int = 16, 78 VmidLength: Int = 14, 79 EnableBPU: Boolean = true, 80 EnableBPD: Boolean = true, 81 EnableRAS: Boolean = true, 82 EnableLB: Boolean = false, 83 EnableLoop: Boolean = true, 84 EnableSC: Boolean = true, 85 EnbaleTlbDebug: Boolean = false, 86 EnableClockGate: Boolean = true, 87 EnableJal: Boolean = false, 88 EnableFauFTB: Boolean = true, 89 UbtbGHRLength: Int = 4, 90 // HistoryLength: Int = 512, 91 EnableGHistDiff: Boolean = true, 92 EnableCommitGHistDiff: Boolean = true, 93 UbtbSize: Int = 256, 94 FtbSize: Int = 2048, 95 RasSize: Int = 16, 96 RasSpecSize: Int = 32, 97 RasCtrSize: Int = 3, 98 CacheLineSize: Int = 512, 99 FtbWays: Int = 4, 100 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 101 // Sets Hist Tag 102 // Seq(( 2048, 2, 8), 103 // ( 2048, 9, 8), 104 // ( 2048, 13, 8), 105 // ( 2048, 20, 8), 106 // ( 2048, 26, 8), 107 // ( 2048, 44, 8), 108 // ( 2048, 73, 8), 109 // ( 2048, 256, 8)), 110 Seq(( 4096, 8, 8), 111 ( 4096, 13, 8), 112 ( 4096, 32, 8), 113 ( 4096, 119, 8)), 114 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 115 // Sets Hist Tag 116 Seq(( 256, 4, 9), 117 ( 256, 8, 9), 118 ( 512, 13, 9), 119 ( 512, 16, 9), 120 ( 512, 32, 9)), 121 SCNRows: Int = 512, 122 SCNTables: Int = 4, 123 SCCtrBits: Int = 6, 124 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 125 numBr: Int = 2, 126 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 127 ((resp_in: BranchPredictionResp, p: Parameters) => { 128 val ftb = Module(new FTB()(p)) 129 val ubtb =Module(new FauFTB()(p)) 130 // val bim = Module(new BIM()(p)) 131 val tage = Module(new Tage_SC()(p)) 132 val ras = Module(new RAS()(p)) 133 val ittage = Module(new ITTage()(p)) 134 val preds = Seq(ubtb, tage, ftb, ittage, ras) 135 preds.map(_.io := DontCare) 136 137 // ubtb.io.resp_in(0) := resp_in 138 // bim.io.resp_in(0) := ubtb.io.resp 139 // btb.io.resp_in(0) := bim.io.resp 140 // tage.io.resp_in(0) := btb.io.resp 141 // loop.io.resp_in(0) := tage.io.resp 142 ubtb.io.in.bits.resp_in(0) := resp_in 143 tage.io.in.bits.resp_in(0) := ubtb.io.out 144 ftb.io.in.bits.resp_in(0) := tage.io.out 145 ittage.io.in.bits.resp_in(0) := ftb.io.out 146 ras.io.in.bits.resp_in(0) := ittage.io.out 147 148 (preds, ras.io.out) 149 }), 150 ICacheECCForceError: Boolean = false, 151 IBufSize: Int = 48, 152 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 153 DecodeWidth: Int = 6, 154 RenameWidth: Int = 6, 155 CommitWidth: Int = 8, 156 RobCommitWidth: Int = 8, 157 RabCommitWidth: Int = 6, 158 MaxUopSize: Int = 65, 159 EnableRenameSnapshot: Boolean = true, 160 RenameSnapshotNum: Int = 4, 161 FtqSize: Int = 64, 162 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 163 IntLogicRegs: Int = 32, 164 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 165 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 166 VCONFIG_IDX: Int = 32, 167 NRPhyRegs: Int = 192, 168 VirtualLoadQueueSize: Int = 72, 169 LoadQueueRARSize: Int = 72, 170 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 171 RollbackGroupSize: Int = 8, 172 LoadQueueReplaySize: Int = 72, 173 LoadUncacheBufferSize: Int = 20, 174 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 175 StoreQueueSize: Int = 64, 176 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 177 StoreQueueForwardWithMask: Boolean = true, 178 VlsQueueSize: Int = 8, 179 RobSize: Int = 160, 180 RabSize: Int = 256, 181 VTypeBufferSize: Int = 64, // used to reorder vtype 182 IssueQueueSize: Int = 24, 183 IssueQueueCompEntrySize: Int = 16, 184 dpParams: DispatchParameters = DispatchParameters( 185 IntDqSize = 16, 186 FpDqSize = 16, 187 LsDqSize = 18, 188 IntDqDeqWidth = 8, 189 FpDqDeqWidth = 6, 190 LsDqDeqWidth = 6, 191 ), 192 intPreg: PregParams = IntPregParams( 193 numEntries = 224, 194 numRead = None, 195 numWrite = None, 196 ), 197 vfPreg: VfPregParams = VfPregParams( 198 numEntries = 192, 199 numRead = None, 200 numWrite = None, 201 ), 202 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 203 LoadPipelineWidth: Int = 3, 204 StorePipelineWidth: Int = 2, 205 VecLoadPipelineWidth: Int = 2, 206 VecStorePipelineWidth: Int = 2, 207 VecMemSrcInWidth: Int = 2, 208 VecMemInstWbWidth: Int = 1, 209 VecMemDispatchWidth: Int = 1, 210 StoreBufferSize: Int = 16, 211 StoreBufferThreshold: Int = 7, 212 EnsbufferWidth: Int = 2, 213 // ============ VLSU ============ 214 UsQueueSize: Int = 8, 215 VlFlowSize: Int = 32, 216 VlUopSize: Int = 32, 217 VsFlowL1Size: Int = 128, 218 VsFlowL2Size: Int = 32, 219 VsUopSize: Int = 32, 220 // ============================== 221 UncacheBufferSize: Int = 4, 222 EnableLoadToLoadForward: Boolean = false, 223 EnableFastForward: Boolean = true, 224 EnableLdVioCheckAfterReset: Boolean = true, 225 EnableSoftPrefetchAfterReset: Boolean = true, 226 EnableCacheErrorAfterReset: Boolean = true, 227 EnableAccurateLoadError: Boolean = true, 228 EnableUncacheWriteOutstanding: Boolean = false, 229 EnableStorePrefetchAtIssue: Boolean = false, 230 EnableStorePrefetchAtCommit: Boolean = false, 231 EnableAtCommitMissTrigger: Boolean = true, 232 EnableStorePrefetchSMS: Boolean = false, 233 EnableStorePrefetchSPB: Boolean = false, 234 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 235 MMUVmidLen: Int = 14, 236 ReSelectLen: Int = 7, // load replay queue replay select counter len 237 iwpuParameters: WPUParameters = WPUParameters( 238 enWPU = false, 239 algoName = "mmru", 240 isICache = true, 241 ), 242 dwpuParameters: WPUParameters = WPUParameters( 243 enWPU = false, 244 algoName = "mmru", 245 enCfPred = false, 246 isICache = false, 247 ), 248 itlbParameters: TLBParameters = TLBParameters( 249 name = "itlb", 250 fetchi = true, 251 useDmode = false, 252 NWays = 48, 253 ), 254 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 255 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 256 ldtlbParameters: TLBParameters = TLBParameters( 257 name = "ldtlb", 258 NWays = 48, 259 outReplace = false, 260 partialStaticPMP = true, 261 outsideRecvFlush = true, 262 saveLevel = true 263 ), 264 sttlbParameters: TLBParameters = TLBParameters( 265 name = "sttlb", 266 NWays = 48, 267 outReplace = false, 268 partialStaticPMP = true, 269 outsideRecvFlush = true, 270 saveLevel = true 271 ), 272 hytlbParameters: TLBParameters = TLBParameters( 273 name = "hytlb", 274 NWays = 48, 275 outReplace = false, 276 partialStaticPMP = true, 277 outsideRecvFlush = true, 278 saveLevel = true 279 ), 280 pftlbParameters: TLBParameters = TLBParameters( 281 name = "pftlb", 282 NWays = 48, 283 outReplace = false, 284 partialStaticPMP = true, 285 outsideRecvFlush = true, 286 saveLevel = true 287 ), 288 refillBothTlb: Boolean = false, 289 btlbParameters: TLBParameters = TLBParameters( 290 name = "btlb", 291 NWays = 48, 292 ), 293 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 294 NumPerfCounters: Int = 16, 295 icacheParameters: ICacheParameters = ICacheParameters( 296 tagECC = Some("parity"), 297 dataECC = Some("parity"), 298 replacer = Some("setplru"), 299 nMissEntries = 2, 300 nProbeEntries = 2, 301 nPrefetchEntries = 12, 302 nPrefBufferEntries = 32, 303 ), 304 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 305 tagECC = Some("secded"), 306 dataECC = Some("secded"), 307 replacer = Some("setplru"), 308 nMissEntries = 16, 309 nProbeEntries = 8, 310 nReleaseEntries = 18, 311 nMaxPrefetchEntry = 6, 312 )), 313 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 314 name = "l2", 315 ways = 8, 316 sets = 1024, // default 512KB L2 317 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 318 )), 319 L2NBanks: Int = 1, 320 usePTWRepeater: Boolean = false, 321 softTLB: Boolean = false, // dpi-c l1tlb debug only 322 softPTW: Boolean = false, // dpi-c l2tlb debug only 323 softPTWDelay: Int = 1 324){ 325 def vlWidth = log2Up(VLEN) + 1 326 327 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 328 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 329 330 val intSchdParams = { 331 implicit val schdType: SchedulerType = IntScheduler() 332 SchdBlockParams(Seq( 333 IssueBlockParams(Seq( 334 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 335 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(7, 1))), true, 2), 336 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 337 IssueBlockParams(Seq( 338 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 339 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 2, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(5, 1))), true, 2), 340 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 341 IssueBlockParams(Seq( 342 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 343 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 3, 1), VfWB(5, 1)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(3, 1)))), 344 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 345 IssueBlockParams(Seq( 346 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 347 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(1, 1)))), 348 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 349 ), 350 numPregs = intPreg.numEntries, 351 numDeqOutside = 0, 352 schdType = schdType, 353 rfDataWidth = intPreg.dataCfg.dataWidth, 354 numUopIn = dpParams.IntDqDeqWidth, 355 ) 356 } 357 val vfSchdParams = { 358 implicit val schdType: SchedulerType = VfScheduler() 359 SchdBlockParams(Seq( 360 IssueBlockParams(Seq( 361 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 362 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 5, 0), IntWB(port = 2, 2)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 363 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 364 IssueBlockParams(Seq( 365 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg, F2vCfg), Seq(VfWB(port = 6, 0)), Seq(Seq(VfRD(7, 1)), Seq(VfRD(8, 1)), Seq(VfRD(9, 1)), Seq(VfRD(5, 1)), Seq(VfRD(6, 1)))), 366 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 7, 0), IntWB(port = 3, 2)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)))), 367 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 368 IssueBlockParams(Seq( 369 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 7, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(0, 2)), Seq(VfRD(1, 2)), Seq(VfRD(2, 2)))), 370 ), numEntries = IssueQueueSize / 2, numEnq = 2, numComp = IssueQueueCompEntrySize / 2), 371 ), 372 numPregs = vfPreg.numEntries, 373 numDeqOutside = 0, 374 schdType = schdType, 375 rfDataWidth = vfPreg.dataCfg.dataWidth, 376 numUopIn = dpParams.FpDqDeqWidth, 377 ) 378 } 379 380 val memSchdParams = { 381 implicit val schdType: SchedulerType = MemScheduler() 382 val rfDataWidth = 64 383 384 SchdBlockParams(Seq( 385 IssueBlockParams(Seq( 386 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(15, 0)))), 387 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 388 IssueBlockParams(Seq( 389 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(13, 1)))), 390 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 391 IssueBlockParams(Seq( 392 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), VfWB(0, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 393 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 394 IssueBlockParams(Seq( 395 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(1, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 396 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 397 IssueBlockParams(Seq( 398 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(2, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 399 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 400 IssueBlockParams(Seq( 401 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(VfRD(12, 0)), Seq(VfRD(13, 0)), Seq(VfRD(14, 0)))), 402 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 403 IssueBlockParams(Seq( 404 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(12, 1), VfRD(12, Int.MaxValue)))), 405 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 406 IssueBlockParams(Seq( 407 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(14, 1), VfRD(13, Int.MaxValue)))), 408 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 409 ), 410 numPregs = intPreg.numEntries max vfPreg.numEntries, 411 numDeqOutside = 0, 412 schdType = schdType, 413 rfDataWidth = rfDataWidth, 414 numUopIn = dpParams.LsDqDeqWidth, 415 ) 416 } 417 418 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 419 420 def iqWakeUpParams = { 421 Seq( 422 WakeUpConfig( 423 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 424 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 425 ), 426 WakeUpConfig( 427 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "LDU0", "LDU1", "LDU2") -> 428 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "VFEX4") 429 ), 430 WakeUpConfig( 431 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 432 Seq("STD0", "STD1") 433 ), 434 ).flatten 435 } 436 437 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 438 439 val backendParams: BackendParams = backend.BackendParams( 440 Map( 441 IntScheduler() -> intSchdParams, 442 VfScheduler() -> vfSchdParams, 443 MemScheduler() -> memSchdParams, 444 ), 445 Seq( 446 intPreg, 447 vfPreg, 448 fakeIntPreg 449 ), 450 iqWakeUpParams, 451 ) 452} 453 454case object DebugOptionsKey extends Field[DebugOptions] 455 456case class DebugOptions 457( 458 FPGAPlatform: Boolean = false, 459 EnableDifftest: Boolean = false, 460 AlwaysBasicDiff: Boolean = true, 461 EnableDebug: Boolean = false, 462 EnablePerfDebug: Boolean = true, 463 UseDRAMSim: Boolean = false, 464 EnableConstantin: Boolean = false, 465 EnableChiselDB: Boolean = false, 466 AlwaysBasicDB: Boolean = true, 467 EnableTopDown: Boolean = false, 468 EnableRollingDB: Boolean = false 469) 470 471trait HasXSParameter { 472 473 implicit val p: Parameters 474 475 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 476 477 val coreParams = p(XSCoreParamsKey) 478 val env = p(DebugOptionsKey) 479 480 val XLEN = coreParams.XLEN 481 val VLEN = coreParams.VLEN 482 val ELEN = coreParams.ELEN 483 val HSXLEN = coreParams.HSXLEN 484 val minFLen = 32 485 val fLen = 64 486 val hartIdLen = p(MaxHartIdBits) 487 def xLen = XLEN 488 489 val HasMExtension = coreParams.HasMExtension 490 val HasCExtension = coreParams.HasCExtension 491 val HasHExtension = coreParams.HasHExtension 492 val HasDiv = coreParams.HasDiv 493 val HasIcache = coreParams.HasICache 494 val HasDcache = coreParams.HasDCache 495 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 496 val GPAddrBits = coreParams.GPAddrBits 497 val VAddrBits = { 498 if(HasHExtension){ 499 coreParams.GPAddrBits 500 }else{ 501 coreParams.VAddrBits 502 } 503 } // VAddrBits is Virtual Memory addr bits 504 505 val AsidLength = coreParams.AsidLength 506 val VmidLength = coreParams.VmidLength 507 val ReSelectLen = coreParams.ReSelectLen 508 val AddrBytes = AddrBits / 8 // unused 509 val DataBits = XLEN 510 val DataBytes = DataBits / 8 511 val VDataBytes = VLEN / 8 512 val HasFPU = coreParams.HasFPU 513 val HasVPU = coreParams.HasVPU 514 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 515 val FetchWidth = coreParams.FetchWidth 516 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 517 val EnableBPU = coreParams.EnableBPU 518 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 519 val EnableRAS = coreParams.EnableRAS 520 val EnableLB = coreParams.EnableLB 521 val EnableLoop = coreParams.EnableLoop 522 val EnableSC = coreParams.EnableSC 523 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 524 val HistoryLength = coreParams.HistoryLength 525 val EnableGHistDiff = coreParams.EnableGHistDiff 526 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 527 val EnableClockGate = coreParams.EnableClockGate 528 val UbtbGHRLength = coreParams.UbtbGHRLength 529 val UbtbSize = coreParams.UbtbSize 530 val EnableFauFTB = coreParams.EnableFauFTB 531 val FtbSize = coreParams.FtbSize 532 val FtbWays = coreParams.FtbWays 533 val RasSize = coreParams.RasSize 534 val RasSpecSize = coreParams.RasSpecSize 535 val RasCtrSize = coreParams.RasCtrSize 536 537 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 538 coreParams.branchPredictor(resp_in, p) 539 } 540 val numBr = coreParams.numBr 541 val TageTableInfos = coreParams.TageTableInfos 542 val TageBanks = coreParams.numBr 543 val SCNRows = coreParams.SCNRows 544 val SCCtrBits = coreParams.SCCtrBits 545 val SCHistLens = coreParams.SCHistLens 546 val SCNTables = coreParams.SCNTables 547 548 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 549 case ((n, cb), h) => (n, cb, h) 550 } 551 val ITTageTableInfos = coreParams.ITTageTableInfos 552 type FoldedHistoryInfo = Tuple2[Int, Int] 553 val foldedGHistInfos = 554 (TageTableInfos.map{ case (nRows, h, t) => 555 if (h > 0) 556 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 557 else 558 Set[FoldedHistoryInfo]() 559 }.reduce(_++_).toSet ++ 560 SCTableInfos.map{ case (nRows, _, h) => 561 if (h > 0) 562 Set((h, min(log2Ceil(nRows/TageBanks), h))) 563 else 564 Set[FoldedHistoryInfo]() 565 }.reduce(_++_).toSet ++ 566 ITTageTableInfos.map{ case (nRows, h, t) => 567 if (h > 0) 568 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 569 else 570 Set[FoldedHistoryInfo]() 571 }.reduce(_++_) ++ 572 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 573 ).toList 574 575 576 577 val CacheLineSize = coreParams.CacheLineSize 578 val CacheLineHalfWord = CacheLineSize / 16 579 val ExtHistoryLength = HistoryLength + 64 580 val ICacheECCForceError = coreParams.ICacheECCForceError 581 val IBufSize = coreParams.IBufSize 582 val IBufNBank = coreParams.IBufNBank 583 val backendParams: BackendParams = coreParams.backendParams 584 val DecodeWidth = coreParams.DecodeWidth 585 val RenameWidth = coreParams.RenameWidth 586 val CommitWidth = coreParams.CommitWidth 587 val RobCommitWidth = coreParams.RobCommitWidth 588 val RabCommitWidth = coreParams.RabCommitWidth 589 val MaxUopSize = coreParams.MaxUopSize 590 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 591 val RenameSnapshotNum = coreParams.RenameSnapshotNum 592 val FtqSize = coreParams.FtqSize 593 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 594 val IntLogicRegs = coreParams.IntLogicRegs 595 val FpLogicRegs = coreParams.FpLogicRegs 596 val VecLogicRegs = coreParams.VecLogicRegs 597 val VCONFIG_IDX = coreParams.VCONFIG_IDX 598 val IntPhyRegs = coreParams.intPreg.numEntries 599 val VfPhyRegs = coreParams.vfPreg.numEntries 600 val MaxPhyPregs = IntPhyRegs max VfPhyRegs 601 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 602 val RobSize = coreParams.RobSize 603 val RabSize = coreParams.RabSize 604 val VTypeBufferSize = coreParams.VTypeBufferSize 605 val IntRefCounterWidth = log2Ceil(RobSize) 606 val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 607 val LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 608 val LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 609 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 610 val LoadQueueRARSize = coreParams.LoadQueueRARSize 611 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 612 val RollbackGroupSize = coreParams.RollbackGroupSize 613 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 614 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 615 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 616 val StoreQueueSize = coreParams.StoreQueueSize 617 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 618 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 619 val VlsQueueSize = coreParams.VlsQueueSize 620 val dpParams = coreParams.dpParams 621 622 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 623 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 624 625 val NumRedirect = backendParams.numRedirect 626 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 627 val FtqRedirectAheadNum = NumRedirect 628 val LoadPipelineWidth = coreParams.LoadPipelineWidth 629 val StorePipelineWidth = coreParams.StorePipelineWidth 630 val VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 631 val VecStorePipelineWidth = coreParams.VecStorePipelineWidth 632 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 633 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 634 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 635 val StoreBufferSize = coreParams.StoreBufferSize 636 val StoreBufferThreshold = coreParams.StoreBufferThreshold 637 val EnsbufferWidth = coreParams.EnsbufferWidth 638 val UsQueueSize = coreParams.UsQueueSize 639 val VlFlowSize = coreParams.VlFlowSize 640 val VlUopSize = coreParams.VlUopSize 641 val VsFlowL1Size = coreParams.VsFlowL1Size 642 val VsFlowL2Size = coreParams.VsFlowL2Size 643 val VsUopSize = coreParams.VsUopSize 644 val UncacheBufferSize = coreParams.UncacheBufferSize 645 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 646 val EnableFastForward = coreParams.EnableFastForward 647 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 648 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 649 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 650 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 651 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 652 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 653 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 654 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 655 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 656 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 657 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 658 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 659 val Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 660 val asidLen = coreParams.MMUAsidLen 661 val vmidLen = coreParams.MMUVmidLen 662 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 663 val refillBothTlb = coreParams.refillBothTlb 664 val iwpuParam = coreParams.iwpuParameters 665 val dwpuParam = coreParams.dwpuParameters 666 val itlbParams = coreParams.itlbParameters 667 val ldtlbParams = coreParams.ldtlbParameters 668 val sttlbParams = coreParams.sttlbParameters 669 val hytlbParams = coreParams.hytlbParameters 670 val pftlbParams = coreParams.pftlbParameters 671 val btlbParams = coreParams.btlbParameters 672 val l2tlbParams = coreParams.l2tlbParameters 673 val NumPerfCounters = coreParams.NumPerfCounters 674 675 val instBytes = if (HasCExtension) 2 else 4 676 val instOffsetBits = log2Ceil(instBytes) 677 678 val icacheParameters = coreParams.icacheParameters 679 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 680 681 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 682 // for constrained LR/SC loop 683 val LRSCCycles = 64 684 // for lr storm 685 val LRSCBackOff = 8 686 687 // cache hierarchy configurations 688 val l1BusDataWidth = 256 689 690 // load violation predict 691 val ResetTimeMax2Pow = 20 //1078576 692 val ResetTimeMin2Pow = 10 //1024 693 // wait table parameters 694 val WaitTableSize = 1024 695 val MemPredPCWidth = log2Up(WaitTableSize) 696 val LWTUse2BitCounter = true 697 // store set parameters 698 val SSITSize = WaitTableSize 699 val LFSTSize = 32 700 val SSIDWidth = log2Up(LFSTSize) 701 val LFSTWidth = 4 702 val StoreSetEnable = true // LWT will be disabled if SS is enabled 703 val LFSTEnable = true 704 705 val PCntIncrStep: Int = 6 706 val numPCntHc: Int = 25 707 val numPCntPtw: Int = 19 708 709 val numCSRPCntFrontend = 8 710 val numCSRPCntCtrl = 8 711 val numCSRPCntLsu = 8 712 val numCSRPCntHc = 5 713 val printEventCoding = true 714 715 // Parameters for Sdtrig extension 716 protected val TriggerNum = 4 717 protected val TriggerChainMaxLength = 2 718} 719