1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams, FakeIntPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import freechips.rocketchip.tile.MaxHartIdBits 42import system.SoCParamsKey 43import huancun._ 44import huancun.debug._ 45import xiangshan.cache.wpu.WPUParameters 46import coupledL2._ 47import xiangshan.backend.datapath.WakeUpConfig 48import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 49 50import scala.math.min 51 52case object XSTileKey extends Field[Seq[XSCoreParameters]] 53 54case object XSCoreParamsKey extends Field[XSCoreParameters] 55 56case class XSCoreParameters 57( 58 HasPrefetch: Boolean = false, 59 HartId: Int = 0, 60 XLEN: Int = 64, 61 VLEN: Int = 128, 62 ELEN: Int = 64, 63 HSXLEN: Int = 64, 64 HasMExtension: Boolean = true, 65 HasCExtension: Boolean = true, 66 HasHExtension: Boolean = true, 67 HasDiv: Boolean = true, 68 HasICache: Boolean = true, 69 HasDCache: Boolean = true, 70 AddrBits: Int = 64, 71 VAddrBits: Int = 39, 72 GPAddrBits: Int = 41, 73 HasFPU: Boolean = true, 74 HasVPU: Boolean = true, 75 HasCustomCSRCacheOp: Boolean = true, 76 FetchWidth: Int = 8, 77 AsidLength: Int = 16, 78 VmidLength: Int = 14, 79 EnableBPU: Boolean = true, 80 EnableBPD: Boolean = true, 81 EnableRAS: Boolean = true, 82 EnableLB: Boolean = false, 83 EnableLoop: Boolean = true, 84 EnableSC: Boolean = true, 85 EnbaleTlbDebug: Boolean = false, 86 EnableClockGate: Boolean = true, 87 EnableJal: Boolean = false, 88 EnableFauFTB: Boolean = true, 89 UbtbGHRLength: Int = 4, 90 // HistoryLength: Int = 512, 91 EnableGHistDiff: Boolean = true, 92 EnableCommitGHistDiff: Boolean = true, 93 UbtbSize: Int = 256, 94 FtbSize: Int = 2048, 95 RasSize: Int = 16, 96 RasSpecSize: Int = 32, 97 RasCtrSize: Int = 3, 98 CacheLineSize: Int = 512, 99 FtbWays: Int = 4, 100 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 101 // Sets Hist Tag 102 // Seq(( 2048, 2, 8), 103 // ( 2048, 9, 8), 104 // ( 2048, 13, 8), 105 // ( 2048, 20, 8), 106 // ( 2048, 26, 8), 107 // ( 2048, 44, 8), 108 // ( 2048, 73, 8), 109 // ( 2048, 256, 8)), 110 Seq(( 4096, 8, 8), 111 ( 4096, 13, 8), 112 ( 4096, 32, 8), 113 ( 4096, 119, 8)), 114 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 115 // Sets Hist Tag 116 Seq(( 256, 4, 9), 117 ( 256, 8, 9), 118 ( 512, 13, 9), 119 ( 512, 16, 9), 120 ( 512, 32, 9)), 121 SCNRows: Int = 512, 122 SCNTables: Int = 4, 123 SCCtrBits: Int = 6, 124 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 125 numBr: Int = 2, 126 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 127 ((resp_in: BranchPredictionResp, p: Parameters) => { 128 val ftb = Module(new FTB()(p)) 129 val ubtb =Module(new FauFTB()(p)) 130 // val bim = Module(new BIM()(p)) 131 val tage = Module(new Tage_SC()(p)) 132 val ras = Module(new RAS()(p)) 133 val ittage = Module(new ITTage()(p)) 134 val preds = Seq(ubtb, tage, ftb, ittage, ras) 135 preds.map(_.io := DontCare) 136 137 // ubtb.io.resp_in(0) := resp_in 138 // bim.io.resp_in(0) := ubtb.io.resp 139 // btb.io.resp_in(0) := bim.io.resp 140 // tage.io.resp_in(0) := btb.io.resp 141 // loop.io.resp_in(0) := tage.io.resp 142 ubtb.io.in.bits.resp_in(0) := resp_in 143 tage.io.in.bits.resp_in(0) := ubtb.io.out 144 ftb.io.in.bits.resp_in(0) := tage.io.out 145 ittage.io.in.bits.resp_in(0) := ftb.io.out 146 ras.io.in.bits.resp_in(0) := ittage.io.out 147 148 (preds, ras.io.out) 149 }), 150 ICacheECCForceError: Boolean = false, 151 IBufSize: Int = 48, 152 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 153 DecodeWidth: Int = 6, 154 RenameWidth: Int = 6, 155 CommitWidth: Int = 8, 156 RobCommitWidth: Int = 8, 157 RabCommitWidth: Int = 6, 158 MaxUopSize: Int = 65, 159 EnableRenameSnapshot: Boolean = true, 160 RenameSnapshotNum: Int = 4, 161 FtqSize: Int = 64, 162 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 163 IntLogicRegs: Int = 32, 164 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 165 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 166 VCONFIG_IDX: Int = 32, 167 NRPhyRegs: Int = 192, 168 VirtualLoadQueueSize: Int = 72, 169 LoadQueueRARSize: Int = 72, 170 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 171 RollbackGroupSize: Int = 8, 172 LoadQueueReplaySize: Int = 72, 173 LoadUncacheBufferSize: Int = 20, 174 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 175 StoreQueueSize: Int = 64, 176 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 177 StoreQueueForwardWithMask: Boolean = true, 178 VlsQueueSize: Int = 8, 179 RobSize: Int = 160, 180 RabSize: Int = 256, 181 VTypeBufferSize: Int = 64, // used to reorder vtype 182 IssueQueueSize: Int = 24, 183 IssueQueueCompEntrySize: Int = 16, 184 dpParams: DispatchParameters = DispatchParameters( 185 IntDqSize = 16, 186 FpDqSize = 16, 187 LsDqSize = 18, 188 IntDqDeqWidth = 8, 189 FpDqDeqWidth = 6, 190 LsDqDeqWidth = 6, 191 ), 192 intPreg: PregParams = IntPregParams( 193 numEntries = 224, 194 numRead = None, 195 numWrite = None, 196 ), 197 vfPreg: VfPregParams = VfPregParams( 198 numEntries = 192, 199 numRead = None, 200 numWrite = None, 201 ), 202 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 203 LoadPipelineWidth: Int = 3, 204 StorePipelineWidth: Int = 2, 205 VecLoadPipelineWidth: Int = 2, 206 VecStorePipelineWidth: Int = 2, 207 VecMemSrcInWidth: Int = 2, 208 VecMemInstWbWidth: Int = 1, 209 VecMemDispatchWidth: Int = 1, 210 StoreBufferSize: Int = 16, 211 StoreBufferThreshold: Int = 7, 212 EnsbufferWidth: Int = 2, 213 LoadDependencyWidth: Int = 2, 214 // ============ VLSU ============ 215 UsQueueSize: Int = 8, 216 VlFlowSize: Int = 32, 217 VlUopSize: Int = 32, 218 VsFlowL1Size: Int = 128, 219 VsFlowL2Size: Int = 32, 220 VsUopSize: Int = 32, 221 // ============================== 222 UncacheBufferSize: Int = 4, 223 EnableLoadToLoadForward: Boolean = false, 224 EnableFastForward: Boolean = true, 225 EnableLdVioCheckAfterReset: Boolean = true, 226 EnableSoftPrefetchAfterReset: Boolean = true, 227 EnableCacheErrorAfterReset: Boolean = true, 228 EnableAccurateLoadError: Boolean = true, 229 EnableUncacheWriteOutstanding: Boolean = false, 230 EnableStorePrefetchAtIssue: Boolean = false, 231 EnableStorePrefetchAtCommit: Boolean = false, 232 EnableAtCommitMissTrigger: Boolean = true, 233 EnableStorePrefetchSMS: Boolean = false, 234 EnableStorePrefetchSPB: Boolean = false, 235 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 236 MMUVmidLen: Int = 14, 237 ReSelectLen: Int = 7, // load replay queue replay select counter len 238 iwpuParameters: WPUParameters = WPUParameters( 239 enWPU = false, 240 algoName = "mmru", 241 isICache = true, 242 ), 243 dwpuParameters: WPUParameters = WPUParameters( 244 enWPU = false, 245 algoName = "mmru", 246 enCfPred = false, 247 isICache = false, 248 ), 249 itlbParameters: TLBParameters = TLBParameters( 250 name = "itlb", 251 fetchi = true, 252 useDmode = false, 253 NWays = 48, 254 ), 255 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 256 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 257 ldtlbParameters: TLBParameters = TLBParameters( 258 name = "ldtlb", 259 NWays = 48, 260 outReplace = false, 261 partialStaticPMP = true, 262 outsideRecvFlush = true, 263 saveLevel = true 264 ), 265 sttlbParameters: TLBParameters = TLBParameters( 266 name = "sttlb", 267 NWays = 48, 268 outReplace = false, 269 partialStaticPMP = true, 270 outsideRecvFlush = true, 271 saveLevel = true 272 ), 273 hytlbParameters: TLBParameters = TLBParameters( 274 name = "hytlb", 275 NWays = 48, 276 outReplace = false, 277 partialStaticPMP = true, 278 outsideRecvFlush = true, 279 saveLevel = true 280 ), 281 pftlbParameters: TLBParameters = TLBParameters( 282 name = "pftlb", 283 NWays = 48, 284 outReplace = false, 285 partialStaticPMP = true, 286 outsideRecvFlush = true, 287 saveLevel = true 288 ), 289 l2ToL1tlbParameters: TLBParameters = TLBParameters( 290 name = "l2tlb", 291 NWays = 48, 292 outReplace = false, 293 partialStaticPMP = true, 294 outsideRecvFlush = true, 295 saveLevel = true 296 ), 297 refillBothTlb: Boolean = false, 298 btlbParameters: TLBParameters = TLBParameters( 299 name = "btlb", 300 NWays = 48, 301 ), 302 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 303 NumPerfCounters: Int = 16, 304 icacheParameters: ICacheParameters = ICacheParameters( 305 tagECC = Some("parity"), 306 dataECC = Some("parity"), 307 replacer = Some("setplru"), 308 nMissEntries = 2, 309 nProbeEntries = 2, 310 nPrefetchEntries = 12, 311 nPrefBufferEntries = 32, 312 ), 313 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 314 tagECC = Some("secded"), 315 dataECC = Some("secded"), 316 replacer = Some("setplru"), 317 nMissEntries = 16, 318 nProbeEntries = 8, 319 nReleaseEntries = 18, 320 nMaxPrefetchEntry = 6, 321 )), 322 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 323 name = "l2", 324 ways = 8, 325 sets = 1024, // default 512KB L2 326 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 327 )), 328 L2NBanks: Int = 1, 329 usePTWRepeater: Boolean = false, 330 softTLB: Boolean = false, // dpi-c l1tlb debug only 331 softPTW: Boolean = false, // dpi-c l2tlb debug only 332 softPTWDelay: Int = 1 333){ 334 def vlWidth = log2Up(VLEN) + 1 335 336 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 337 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 338 339 val intSchdParams = { 340 implicit val schdType: SchedulerType = IntScheduler() 341 SchdBlockParams(Seq( 342 IssueBlockParams(Seq( 343 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 344 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(7, 1))), true, 2), 345 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 346 IssueBlockParams(Seq( 347 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 348 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 2, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(5, 1))), true, 2), 349 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 350 IssueBlockParams(Seq( 351 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 352 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 3, 1), VfWB(5, 1)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(3, 1)))), 353 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 354 IssueBlockParams(Seq( 355 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 356 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(1, 1)))), 357 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 358 ), 359 numPregs = intPreg.numEntries, 360 numDeqOutside = 0, 361 schdType = schdType, 362 rfDataWidth = intPreg.dataCfg.dataWidth, 363 numUopIn = dpParams.IntDqDeqWidth, 364 ) 365 } 366 val vfSchdParams = { 367 implicit val schdType: SchedulerType = VfScheduler() 368 SchdBlockParams(Seq( 369 IssueBlockParams(Seq( 370 ExeUnitParams("VFEX0", Seq(VfmaCfg, VialuCfg, VimacCfg, VppuCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 371 ExeUnitParams("VFEX1", Seq(VfaluCfg, VfcvtCfg, VipuCfg, VSetRvfWvfCfg), Seq(VfWB(port = 5, 0), IntWB(port = 2, 2)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 372 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 373 IssueBlockParams(Seq( 374 ExeUnitParams("VFEX2", Seq(VfmaCfg, VialuCfg, F2vCfg), Seq(VfWB(port = 6, 0)), Seq(Seq(VfRD(7, 1)), Seq(VfRD(8, 1)), Seq(VfRD(9, 1)), Seq(VfRD(5, 1)), Seq(VfRD(6, 1)))), 375 ExeUnitParams("VFEX3", Seq(VfaluCfg, VfcvtCfg), Seq(VfWB(port = 7, 0), IntWB(port = 3, 2)), Seq(Seq(VfRD(3, 1)), Seq(VfRD(4, 1)), Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)))), 376 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 377 IssueBlockParams(Seq( 378 ExeUnitParams("VFEX4", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 7, 1)), Seq(Seq(VfRD(3, 2)), Seq(VfRD(4, 2)), Seq(VfRD(0, 2)), Seq(VfRD(1, 2)), Seq(VfRD(2, 2)))), 379 ExeUnitParams("VFEX5", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 6, 1)), Seq(Seq(VfRD(8, 2)), Seq(VfRD(9, 2)), Seq(VfRD(5, 2)), Seq(VfRD(6, 2)), Seq(VfRD(7, 2)))), 380 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 381 ), 382 numPregs = vfPreg.numEntries, 383 numDeqOutside = 0, 384 schdType = schdType, 385 rfDataWidth = vfPreg.dataCfg.dataWidth, 386 numUopIn = dpParams.FpDqDeqWidth, 387 ) 388 } 389 390 val memSchdParams = { 391 implicit val schdType: SchedulerType = MemScheduler() 392 val rfDataWidth = 64 393 394 SchdBlockParams(Seq( 395 IssueBlockParams(Seq( 396 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(8, 1)))), 397 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 398 IssueBlockParams(Seq( 399 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(9, 1)))), 400 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 401 IssueBlockParams(Seq( 402 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), VfWB(0, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 403 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 404 IssueBlockParams(Seq( 405 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(1, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 406 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 407 IssueBlockParams(Seq( 408 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(2, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 409 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 410 IssueBlockParams(Seq( 411 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(VfRD(12, 0)), Seq(VfRD(13, 0)), Seq(VfRD(14, 0)))), 412 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 413 IssueBlockParams(Seq( 414 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(10, 1), VfRD(12, Int.MaxValue)))), 415 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 416 IssueBlockParams(Seq( 417 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(11, 1), VfRD(13, Int.MaxValue)))), 418 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 419 ), 420 numPregs = intPreg.numEntries max vfPreg.numEntries, 421 numDeqOutside = 0, 422 schdType = schdType, 423 rfDataWidth = rfDataWidth, 424 numUopIn = dpParams.LsDqDeqWidth, 425 ) 426 } 427 428 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 429 430 def iqWakeUpParams = { 431 Seq( 432 WakeUpConfig( 433 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 434 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 435 ), 436 WakeUpConfig( 437 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "LDU0", "LDU1", "LDU2") -> 438 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3", "VFEX4", "VFEX5") 439 ), 440 WakeUpConfig( 441 Seq("VFEX0", "VFEX1", "VFEX2", "VFEX3") -> 442 Seq("STD0", "STD1") 443 ), 444 ).flatten 445 } 446 447 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 448 449 val backendParams: BackendParams = backend.BackendParams( 450 Map( 451 IntScheduler() -> intSchdParams, 452 VfScheduler() -> vfSchdParams, 453 MemScheduler() -> memSchdParams, 454 ), 455 Seq( 456 intPreg, 457 vfPreg, 458 fakeIntPreg 459 ), 460 iqWakeUpParams, 461 ) 462} 463 464case object DebugOptionsKey extends Field[DebugOptions] 465 466case class DebugOptions 467( 468 FPGAPlatform: Boolean = false, 469 EnableDifftest: Boolean = false, 470 AlwaysBasicDiff: Boolean = true, 471 EnableDebug: Boolean = false, 472 EnablePerfDebug: Boolean = true, 473 UseDRAMSim: Boolean = false, 474 EnableConstantin: Boolean = false, 475 EnableChiselDB: Boolean = false, 476 AlwaysBasicDB: Boolean = true, 477 EnableTopDown: Boolean = false, 478 EnableRollingDB: Boolean = false 479) 480 481trait HasXSParameter { 482 483 implicit val p: Parameters 484 485 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 486 487 val coreParams = p(XSCoreParamsKey) 488 val env = p(DebugOptionsKey) 489 490 val XLEN = coreParams.XLEN 491 val VLEN = coreParams.VLEN 492 val ELEN = coreParams.ELEN 493 val HSXLEN = coreParams.HSXLEN 494 val minFLen = 32 495 val fLen = 64 496 val hartIdLen = p(MaxHartIdBits) 497 def xLen = XLEN 498 499 val HasMExtension = coreParams.HasMExtension 500 val HasCExtension = coreParams.HasCExtension 501 val HasHExtension = coreParams.HasHExtension 502 val HasDiv = coreParams.HasDiv 503 val HasIcache = coreParams.HasICache 504 val HasDcache = coreParams.HasDCache 505 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 506 val GPAddrBits = coreParams.GPAddrBits 507 val VAddrBits = { 508 if(HasHExtension){ 509 coreParams.GPAddrBits 510 }else{ 511 coreParams.VAddrBits 512 } 513 } // VAddrBits is Virtual Memory addr bits 514 515 val AsidLength = coreParams.AsidLength 516 val VmidLength = coreParams.VmidLength 517 val ReSelectLen = coreParams.ReSelectLen 518 val AddrBytes = AddrBits / 8 // unused 519 val DataBits = XLEN 520 val DataBytes = DataBits / 8 521 val VDataBytes = VLEN / 8 522 val HasFPU = coreParams.HasFPU 523 val HasVPU = coreParams.HasVPU 524 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 525 val FetchWidth = coreParams.FetchWidth 526 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 527 val EnableBPU = coreParams.EnableBPU 528 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 529 val EnableRAS = coreParams.EnableRAS 530 val EnableLB = coreParams.EnableLB 531 val EnableLoop = coreParams.EnableLoop 532 val EnableSC = coreParams.EnableSC 533 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 534 val HistoryLength = coreParams.HistoryLength 535 val EnableGHistDiff = coreParams.EnableGHistDiff 536 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 537 val EnableClockGate = coreParams.EnableClockGate 538 val UbtbGHRLength = coreParams.UbtbGHRLength 539 val UbtbSize = coreParams.UbtbSize 540 val EnableFauFTB = coreParams.EnableFauFTB 541 val FtbSize = coreParams.FtbSize 542 val FtbWays = coreParams.FtbWays 543 val RasSize = coreParams.RasSize 544 val RasSpecSize = coreParams.RasSpecSize 545 val RasCtrSize = coreParams.RasCtrSize 546 547 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 548 coreParams.branchPredictor(resp_in, p) 549 } 550 val numBr = coreParams.numBr 551 val TageTableInfos = coreParams.TageTableInfos 552 val TageBanks = coreParams.numBr 553 val SCNRows = coreParams.SCNRows 554 val SCCtrBits = coreParams.SCCtrBits 555 val SCHistLens = coreParams.SCHistLens 556 val SCNTables = coreParams.SCNTables 557 558 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 559 case ((n, cb), h) => (n, cb, h) 560 } 561 val ITTageTableInfos = coreParams.ITTageTableInfos 562 type FoldedHistoryInfo = Tuple2[Int, Int] 563 val foldedGHistInfos = 564 (TageTableInfos.map{ case (nRows, h, t) => 565 if (h > 0) 566 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 567 else 568 Set[FoldedHistoryInfo]() 569 }.reduce(_++_).toSet ++ 570 SCTableInfos.map{ case (nRows, _, h) => 571 if (h > 0) 572 Set((h, min(log2Ceil(nRows/TageBanks), h))) 573 else 574 Set[FoldedHistoryInfo]() 575 }.reduce(_++_).toSet ++ 576 ITTageTableInfos.map{ case (nRows, h, t) => 577 if (h > 0) 578 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 579 else 580 Set[FoldedHistoryInfo]() 581 }.reduce(_++_) ++ 582 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 583 ).toList 584 585 586 587 val CacheLineSize = coreParams.CacheLineSize 588 val CacheLineHalfWord = CacheLineSize / 16 589 val ExtHistoryLength = HistoryLength + 64 590 val ICacheECCForceError = coreParams.ICacheECCForceError 591 val IBufSize = coreParams.IBufSize 592 val IBufNBank = coreParams.IBufNBank 593 val backendParams: BackendParams = coreParams.backendParams 594 val DecodeWidth = coreParams.DecodeWidth 595 val RenameWidth = coreParams.RenameWidth 596 val CommitWidth = coreParams.CommitWidth 597 val RobCommitWidth = coreParams.RobCommitWidth 598 val RabCommitWidth = coreParams.RabCommitWidth 599 val MaxUopSize = coreParams.MaxUopSize 600 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 601 val RenameSnapshotNum = coreParams.RenameSnapshotNum 602 val FtqSize = coreParams.FtqSize 603 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 604 val IntLogicRegs = coreParams.IntLogicRegs 605 val FpLogicRegs = coreParams.FpLogicRegs 606 val VecLogicRegs = coreParams.VecLogicRegs 607 val VCONFIG_IDX = coreParams.VCONFIG_IDX 608 val IntPhyRegs = coreParams.intPreg.numEntries 609 val VfPhyRegs = coreParams.vfPreg.numEntries 610 val MaxPhyPregs = IntPhyRegs max VfPhyRegs 611 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 612 val RobSize = coreParams.RobSize 613 val RabSize = coreParams.RabSize 614 val VTypeBufferSize = coreParams.VTypeBufferSize 615 val IntRefCounterWidth = log2Ceil(RobSize) 616 val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 617 val LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 618 val LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 619 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 620 val LoadQueueRARSize = coreParams.LoadQueueRARSize 621 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 622 val RollbackGroupSize = coreParams.RollbackGroupSize 623 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 624 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 625 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 626 val StoreQueueSize = coreParams.StoreQueueSize 627 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 628 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 629 val VlsQueueSize = coreParams.VlsQueueSize 630 val dpParams = coreParams.dpParams 631 632 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 633 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 634 635 val NumRedirect = backendParams.numRedirect 636 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 637 val FtqRedirectAheadNum = NumRedirect 638 val LoadPipelineWidth = coreParams.LoadPipelineWidth 639 val StorePipelineWidth = coreParams.StorePipelineWidth 640 val VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 641 val VecStorePipelineWidth = coreParams.VecStorePipelineWidth 642 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 643 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 644 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 645 val StoreBufferSize = coreParams.StoreBufferSize 646 val StoreBufferThreshold = coreParams.StoreBufferThreshold 647 val EnsbufferWidth = coreParams.EnsbufferWidth 648 val LoadDependencyWidth = coreParams.LoadDependencyWidth 649 val UsQueueSize = coreParams.UsQueueSize 650 val VlFlowSize = coreParams.VlFlowSize 651 val VlUopSize = coreParams.VlUopSize 652 val VsFlowL1Size = coreParams.VsFlowL1Size 653 val VsFlowL2Size = coreParams.VsFlowL2Size 654 val VsUopSize = coreParams.VsUopSize 655 val UncacheBufferSize = coreParams.UncacheBufferSize 656 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 657 val EnableFastForward = coreParams.EnableFastForward 658 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 659 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 660 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 661 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 662 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 663 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 664 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 665 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 666 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 667 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 668 require(LoadPipelineWidth == backendParams.LdExuCnt, "LoadPipelineWidth must be equal exuParameters.LduCnt!") 669 require(StorePipelineWidth == backendParams.StaCnt, "StorePipelineWidth must be equal exuParameters.StuCnt!") 670 val Enable3Load3Store = (LoadPipelineWidth == 3 && StorePipelineWidth == 3) 671 val asidLen = coreParams.MMUAsidLen 672 val vmidLen = coreParams.MMUVmidLen 673 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 674 val refillBothTlb = coreParams.refillBothTlb 675 val iwpuParam = coreParams.iwpuParameters 676 val dwpuParam = coreParams.dwpuParameters 677 val itlbParams = coreParams.itlbParameters 678 val ldtlbParams = coreParams.ldtlbParameters 679 val sttlbParams = coreParams.sttlbParameters 680 val hytlbParams = coreParams.hytlbParameters 681 val pftlbParams = coreParams.pftlbParameters 682 val l2ToL1Params = coreParams.l2ToL1tlbParameters 683 val btlbParams = coreParams.btlbParameters 684 val l2tlbParams = coreParams.l2tlbParameters 685 val NumPerfCounters = coreParams.NumPerfCounters 686 687 val instBytes = if (HasCExtension) 2 else 4 688 val instOffsetBits = log2Ceil(instBytes) 689 690 val icacheParameters = coreParams.icacheParameters 691 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 692 693 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 694 // for constrained LR/SC loop 695 val LRSCCycles = 64 696 // for lr storm 697 val LRSCBackOff = 8 698 699 // cache hierarchy configurations 700 val l1BusDataWidth = 256 701 702 // load violation predict 703 val ResetTimeMax2Pow = 20 //1078576 704 val ResetTimeMin2Pow = 10 //1024 705 // wait table parameters 706 val WaitTableSize = 1024 707 val MemPredPCWidth = log2Up(WaitTableSize) 708 val LWTUse2BitCounter = true 709 // store set parameters 710 val SSITSize = WaitTableSize 711 val LFSTSize = 32 712 val SSIDWidth = log2Up(LFSTSize) 713 val LFSTWidth = 4 714 val StoreSetEnable = true // LWT will be disabled if SS is enabled 715 val LFSTEnable = true 716 717 val PCntIncrStep: Int = 6 718 val numPCntHc: Int = 25 719 val numPCntPtw: Int = 19 720 721 val numCSRPCntFrontend = 8 722 val numCSRPCntCtrl = 8 723 val numCSRPCntLsu = 8 724 val numCSRPCntHc = 5 725 val printEventCoding = true 726 727 // Parameters for Sdtrig extension 728 protected val TriggerNum = 4 729 protected val TriggerChainMaxLength = 2 730} 731