1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import org.chipsalliance.cde.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams, FakeIntPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import xiangshan.cache.wpu.WPUParameters 45import coupledL2._ 46import xiangshan.backend.datapath.WakeUpConfig 47import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 48 49import scala.math.min 50 51case object XSTileKey extends Field[Seq[XSCoreParameters]] 52 53case object XSCoreParamsKey extends Field[XSCoreParameters] 54 55case class XSCoreParameters 56( 57 HasPrefetch: Boolean = false, 58 HartId: Int = 0, 59 XLEN: Int = 64, 60 VLEN: Int = 128, 61 ELEN: Int = 64, 62 HasMExtension: Boolean = true, 63 HasCExtension: Boolean = true, 64 HasDiv: Boolean = true, 65 HasICache: Boolean = true, 66 HasDCache: Boolean = true, 67 AddrBits: Int = 64, 68 VAddrBits: Int = 39, 69 HasFPU: Boolean = true, 70 HasVPU: Boolean = true, 71 HasCustomCSRCacheOp: Boolean = true, 72 FetchWidth: Int = 8, 73 AsidLength: Int = 16, 74 EnableBPU: Boolean = true, 75 EnableBPD: Boolean = true, 76 EnableRAS: Boolean = true, 77 EnableLB: Boolean = false, 78 EnableLoop: Boolean = true, 79 EnableSC: Boolean = true, 80 EnbaleTlbDebug: Boolean = false, 81 EnableClockGate: Boolean = true, 82 EnableJal: Boolean = false, 83 EnableFauFTB: Boolean = true, 84 UbtbGHRLength: Int = 4, 85 // HistoryLength: Int = 512, 86 EnableGHistDiff: Boolean = true, 87 EnableCommitGHistDiff: Boolean = true, 88 UbtbSize: Int = 256, 89 FtbSize: Int = 2048, 90 RasSize: Int = 16, 91 RasSpecSize: Int = 32, 92 RasCtrSize: Int = 3, 93 CacheLineSize: Int = 512, 94 FtbWays: Int = 4, 95 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 96 // Sets Hist Tag 97 // Seq(( 2048, 2, 8), 98 // ( 2048, 9, 8), 99 // ( 2048, 13, 8), 100 // ( 2048, 20, 8), 101 // ( 2048, 26, 8), 102 // ( 2048, 44, 8), 103 // ( 2048, 73, 8), 104 // ( 2048, 256, 8)), 105 Seq(( 4096, 8, 8), 106 ( 4096, 13, 8), 107 ( 4096, 32, 8), 108 ( 4096, 119, 8)), 109 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 110 // Sets Hist Tag 111 Seq(( 256, 4, 9), 112 ( 256, 8, 9), 113 ( 512, 13, 9), 114 ( 512, 16, 9), 115 ( 512, 32, 9)), 116 SCNRows: Int = 512, 117 SCNTables: Int = 4, 118 SCCtrBits: Int = 6, 119 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 120 numBr: Int = 2, 121 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 122 ((resp_in: BranchPredictionResp, p: Parameters) => { 123 val ftb = Module(new FTB()(p)) 124 val ubtb =Module(new FauFTB()(p)) 125 // val bim = Module(new BIM()(p)) 126 val tage = Module(new Tage_SC()(p)) 127 val ras = Module(new RAS()(p)) 128 val ittage = Module(new ITTage()(p)) 129 val preds = Seq(ubtb, tage, ftb, ittage, ras) 130 preds.map(_.io := DontCare) 131 132 // ubtb.io.resp_in(0) := resp_in 133 // bim.io.resp_in(0) := ubtb.io.resp 134 // btb.io.resp_in(0) := bim.io.resp 135 // tage.io.resp_in(0) := btb.io.resp 136 // loop.io.resp_in(0) := tage.io.resp 137 ubtb.io.in.bits.resp_in(0) := resp_in 138 tage.io.in.bits.resp_in(0) := ubtb.io.out 139 ftb.io.in.bits.resp_in(0) := tage.io.out 140 ittage.io.in.bits.resp_in(0) := ftb.io.out 141 ras.io.in.bits.resp_in(0) := ittage.io.out 142 143 (preds, ras.io.out) 144 }), 145 ICacheECCForceError: Boolean = false, 146 IBufSize: Int = 48, 147 IBufNBank: Int = 6, // IBuffer bank amount, should divide IBufSize 148 DecodeWidth: Int = 6, 149 RenameWidth: Int = 6, 150 CommitWidth: Int = 6, 151 MaxUopSize: Int = 65, 152 EnableRenameSnapshot: Boolean = true, 153 RenameSnapshotNum: Int = 4, 154 FtqSize: Int = 64, 155 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 156 IntLogicRegs: Int = 32, 157 FpLogicRegs: Int = 32 + 1 + 1, // 1: I2F, 1: stride 158 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 159 VCONFIG_IDX: Int = 32, 160 NRPhyRegs: Int = 192, 161 VirtualLoadQueueSize: Int = 72, 162 LoadQueueRARSize: Int = 72, 163 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 164 RollbackGroupSize: Int = 8, 165 LoadQueueReplaySize: Int = 72, 166 LoadUncacheBufferSize: Int = 20, 167 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 168 StoreQueueSize: Int = 64, 169 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 170 StoreQueueForwardWithMask: Boolean = true, 171 VlsQueueSize: Int = 8, 172 RobSize: Int = 160, 173 RabSize: Int = 256, 174 VTypeBufferSize: Int = 64, // used to reorder vtype 175 IssueQueueSize: Int = 24, 176 IssueQueueCompEntrySize: Int = 16, 177 dpParams: DispatchParameters = DispatchParameters( 178 IntDqSize = 16, 179 FpDqSize = 16, 180 LsDqSize = 18, 181 IntDqDeqWidth = 8, 182 FpDqDeqWidth = 6, 183 LsDqDeqWidth = 6, 184 ), 185 intPreg: PregParams = IntPregParams( 186 numEntries = 224, 187 numRead = None, 188 numWrite = None, 189 ), 190 vfPreg: VfPregParams = VfPregParams( 191 numEntries = 192, 192 numRead = None, 193 numWrite = None, 194 ), 195 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 196 LoadPipelineWidth: Int = 3, 197 StorePipelineWidth: Int = 2, 198 VecLoadPipelineWidth: Int = 1, 199 VecStorePipelineWidth: Int = 1, 200 VecMemSrcInWidth: Int = 2, 201 VecMemInstWbWidth: Int = 1, 202 VecMemDispatchWidth: Int = 1, 203 VecMemDispatchMaxNumber: Int = 16, 204 StoreBufferSize: Int = 16, 205 StoreBufferThreshold: Int = 7, 206 EnsbufferWidth: Int = 2, 207 // ============ VLSU ============ 208 VlMergeBufferSize: Int = 16, 209 VsMergeBufferSize: Int = 16, 210 UopWritebackWidth: Int = 1, 211 SplitBufferSize: Int = 8, 212 // ============================== 213 UncacheBufferSize: Int = 4, 214 EnableLoadToLoadForward: Boolean = false, 215 EnableFastForward: Boolean = true, 216 EnableLdVioCheckAfterReset: Boolean = true, 217 EnableSoftPrefetchAfterReset: Boolean = true, 218 EnableCacheErrorAfterReset: Boolean = true, 219 EnableAccurateLoadError: Boolean = true, 220 EnableUncacheWriteOutstanding: Boolean = false, 221 EnableStorePrefetchAtIssue: Boolean = false, 222 EnableStorePrefetchAtCommit: Boolean = false, 223 EnableAtCommitMissTrigger: Boolean = true, 224 EnableStorePrefetchSMS: Boolean = false, 225 EnableStorePrefetchSPB: Boolean = false, 226 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 227 ReSelectLen: Int = 7, // load replay queue replay select counter len 228 iwpuParameters: WPUParameters = WPUParameters( 229 enWPU = false, 230 algoName = "mmru", 231 isICache = true, 232 ), 233 dwpuParameters: WPUParameters = WPUParameters( 234 enWPU = false, 235 algoName = "mmru", 236 enCfPred = false, 237 isICache = false, 238 ), 239 itlbParameters: TLBParameters = TLBParameters( 240 name = "itlb", 241 fetchi = true, 242 useDmode = false, 243 NWays = 48, 244 ), 245 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 246 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 247 ldtlbParameters: TLBParameters = TLBParameters( 248 name = "ldtlb", 249 NWays = 48, 250 outReplace = false, 251 partialStaticPMP = true, 252 outsideRecvFlush = true, 253 saveLevel = true, 254 lgMaxSize = 4 255 ), 256 sttlbParameters: TLBParameters = TLBParameters( 257 name = "sttlb", 258 NWays = 48, 259 outReplace = false, 260 partialStaticPMP = true, 261 outsideRecvFlush = true, 262 saveLevel = true, 263 lgMaxSize = 4 264 ), 265 hytlbParameters: TLBParameters = TLBParameters( 266 name = "hytlb", 267 NWays = 48, 268 outReplace = false, 269 partialStaticPMP = true, 270 outsideRecvFlush = true, 271 saveLevel = true, 272 lgMaxSize = 4 273 ), 274 pftlbParameters: TLBParameters = TLBParameters( 275 name = "pftlb", 276 NWays = 48, 277 outReplace = false, 278 partialStaticPMP = true, 279 outsideRecvFlush = true, 280 saveLevel = true, 281 lgMaxSize = 4 282 ), 283 refillBothTlb: Boolean = false, 284 btlbParameters: TLBParameters = TLBParameters( 285 name = "btlb", 286 NWays = 48, 287 ), 288 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 289 NumPerfCounters: Int = 16, 290 icacheParameters: ICacheParameters = ICacheParameters( 291 tagECC = Some("parity"), 292 dataECC = Some("parity"), 293 replacer = Some("setplru"), 294 nMissEntries = 2, 295 nProbeEntries = 2, 296 nPrefetchEntries = 12, 297 nPrefBufferEntries = 32, 298 ), 299 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 300 tagECC = Some("secded"), 301 dataECC = Some("secded"), 302 replacer = Some("setplru"), 303 nMissEntries = 16, 304 nProbeEntries = 8, 305 nReleaseEntries = 18, 306 nMaxPrefetchEntry = 6, 307 )), 308 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 309 name = "l2", 310 ways = 8, 311 sets = 1024, // default 512KB L2 312 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 313 )), 314 L2NBanks: Int = 1, 315 usePTWRepeater: Boolean = false, 316 softTLB: Boolean = false, // dpi-c l1tlb debug only 317 softPTW: Boolean = false, // dpi-c l2tlb debug only 318 softPTWDelay: Int = 1 319){ 320 def vlWidth = log2Up(VLEN) + 1 321 322 /** 323 * the minimum element length of vector elements 324 */ 325 val minVecElen: Int = 8 326 327 /** 328 * the maximum number of elements in vector register 329 */ 330 val maxElemPerVreg: Int = VLEN / minVecElen 331 332 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 333 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 334 335 val intSchdParams = { 336 implicit val schdType: SchedulerType = IntScheduler() 337 SchdBlockParams(Seq( 338 IssueBlockParams(Seq( 339 ExeUnitParams("ALU0", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0))), true, 2), 340 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(7, 1))), true, 2), 341 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 342 IssueBlockParams(Seq( 343 ExeUnitParams("ALU1", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0))), true, 2), 344 ExeUnitParams("BJU1", Seq(BrhCfg, JmpCfg), Seq(IntWB(port = 2, 1)), Seq(Seq(IntRD(9, 0)), Seq(IntRD(5, 1))), true, 2), 345 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 346 IssueBlockParams(Seq( 347 ExeUnitParams("ALU2", Seq(AluCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0))), true, 2), 348 ExeUnitParams("BJU2", Seq(BrhCfg, JmpCfg, I2fCfg, VSetRiWiCfg, VSetRiWvfCfg, CsrCfg, FenceCfg, I2vCfg), Seq(IntWB(port = 3, 1), VfWB(4, 0)), Seq(Seq(IntRD(10, 0)), Seq(IntRD(3, 1)))), 349 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 350 IssueBlockParams(Seq( 351 ExeUnitParams("ALU3", Seq(AluCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0))), true, 2), 352 ExeUnitParams("BJU3", Seq(DivCfg), Seq(IntWB(port = 4, 1)), Seq(Seq(IntRD(11, 0)), Seq(IntRD(1, 1)))), 353 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 354 ), 355 numPregs = intPreg.numEntries, 356 numDeqOutside = 0, 357 schdType = schdType, 358 rfDataWidth = intPreg.dataCfg.dataWidth, 359 numUopIn = dpParams.IntDqDeqWidth, 360 ) 361 } 362 val vfSchdParams = { 363 implicit val schdType: SchedulerType = VfScheduler() 364 SchdBlockParams(Seq( 365 IssueBlockParams(Seq( 366 ExeUnitParams("VFEX0", Seq(VfaluCfg, VfmaCfg, VialuCfg, VimacCfg), Seq(VfWB(port = 5, 0), IntWB(port = 0, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 367 ExeUnitParams("VFEX1", Seq(VipuCfg, VppuCfg, VfcvtCfg, F2vCfg, VSetRvfWvfCfg), Seq(VfWB(port = 6, 1), IntWB(port = 1, 2)), Seq(Seq(VfRD(5, 1)), Seq(VfRD(6, 1)), Seq(VfRD(7, 1)), Seq(VfRD(8, 1)), Seq(VfRD(9, 1)))), 368 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 369 IssueBlockParams(Seq( 370 ExeUnitParams("VFEX2", Seq(VfaluCfg, VfmaCfg, VialuCfg), Seq(VfWB(port = 6, 0), IntWB(port = 1, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 371 ExeUnitParams("VFEX3", Seq(VfdivCfg, VidivCfg), Seq(VfWB(port = 5, 1)), Seq(Seq(VfRD(0, 1)), Seq(VfRD(1, 1)), Seq(VfRD(2, 1)), Seq(VfRD(3, 1)), Seq(VfRD(4, 1)))), 372 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 373 ), 374 numPregs = vfPreg.numEntries, 375 numDeqOutside = 0, 376 schdType = schdType, 377 rfDataWidth = vfPreg.dataCfg.dataWidth, 378 numUopIn = dpParams.FpDqDeqWidth, 379 ) 380 } 381 382 val memSchdParams = { 383 implicit val schdType: SchedulerType = MemScheduler() 384 val rfDataWidth = 64 385 386 SchdBlockParams(Seq( 387 IssueBlockParams(Seq( 388 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(15, 0)))), 389 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 390 IssueBlockParams(Seq( 391 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(FakeIntWB()), Seq(Seq(IntRD(13, 1)))), 392 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 393 IssueBlockParams(Seq( 394 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(5, 0), VfWB(0, 0)), Seq(Seq(IntRD(12, 0))), true, 2), 395 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 396 IssueBlockParams(Seq( 397 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(1, 0)), Seq(Seq(IntRD(13, 0))), true, 2), 398 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 399 IssueBlockParams(Seq( 400 ExeUnitParams("LDU2", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(2, 0)), Seq(Seq(IntRD(14, 0))), true, 2), 401 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 402 IssueBlockParams(Seq( 403 ExeUnitParams("VLSU0", Seq(VlduCfg, VstuCfg), Seq(VfWB(3, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)), Seq(VfRD(12, 0)), Seq(VfRD(13, 0)), Seq(VfRD(14, 0)))), 404 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 405 IssueBlockParams(Seq( 406 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(12, 1), VfRD(12, Int.MaxValue)))), 407 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 408 IssueBlockParams(Seq( 409 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(14, 1), VfRD(13, Int.MaxValue)))), 410 ), numEntries = IssueQueueSize, numEnq = 2, numComp = IssueQueueCompEntrySize), 411 ), 412 numPregs = intPreg.numEntries max vfPreg.numEntries, 413 numDeqOutside = 0, 414 schdType = schdType, 415 rfDataWidth = rfDataWidth, 416 numUopIn = dpParams.LsDqDeqWidth, 417 ) 418 } 419 420 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 421 422 def iqWakeUpParams = { 423 Seq( 424 WakeUpConfig( 425 Seq("ALU0", "ALU1", "ALU2", "ALU3", "LDU0", "LDU1", "LDU2") -> 426 Seq("ALU0", "BJU0", "ALU1", "BJU1", "ALU2", "BJU2", "ALU3", "BJU3", "LDU0", "LDU1", "LDU2", "STA0", "STA1", "STD0", "STD1") 427 ), 428 WakeUpConfig( 429 Seq("VFEX0", "VFEX1", "VFEX2") -> 430 Seq("VFEX0", "VFEX1", "VFEX2") 431 ), 432 ).flatten 433 } 434 435 def fakeIntPreg = FakeIntPregParams(intPreg.numEntries, intPreg.numRead, intPreg.numWrite) 436 437 val backendParams: BackendParams = backend.BackendParams( 438 Map( 439 IntScheduler() -> intSchdParams, 440 VfScheduler() -> vfSchdParams, 441 MemScheduler() -> memSchdParams, 442 ), 443 Seq( 444 intPreg, 445 vfPreg, 446 fakeIntPreg 447 ), 448 iqWakeUpParams, 449 ) 450} 451 452case object DebugOptionsKey extends Field[DebugOptions] 453 454case class DebugOptions 455( 456 FPGAPlatform: Boolean = false, 457 EnableDifftest: Boolean = false, 458 AlwaysBasicDiff: Boolean = true, 459 EnableDebug: Boolean = false, 460 EnablePerfDebug: Boolean = true, 461 UseDRAMSim: Boolean = false, 462 EnableConstantin: Boolean = false, 463 EnableChiselDB: Boolean = false, 464 AlwaysBasicDB: Boolean = true, 465 EnableTopDown: Boolean = false, 466 EnableRollingDB: Boolean = false 467) 468 469trait HasXSParameter { 470 471 implicit val p: Parameters 472 473 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 474 475 val coreParams = p(XSCoreParamsKey) 476 val env = p(DebugOptionsKey) 477 478 val XLEN = coreParams.XLEN 479 val VLEN = coreParams.VLEN 480 val ELEN = coreParams.ELEN 481 val minFLen = 32 482 val fLen = 64 483 def xLen = XLEN 484 485 val HasMExtension = coreParams.HasMExtension 486 val HasCExtension = coreParams.HasCExtension 487 val HasDiv = coreParams.HasDiv 488 val HasIcache = coreParams.HasICache 489 val HasDcache = coreParams.HasDCache 490 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 491 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 492 val AsidLength = coreParams.AsidLength 493 val ReSelectLen = coreParams.ReSelectLen 494 val AddrBytes = AddrBits / 8 // unused 495 val DataBits = XLEN 496 val DataBytes = DataBits / 8 497 val VDataBytes = VLEN / 8 498 val HasFPU = coreParams.HasFPU 499 val HasVPU = coreParams.HasVPU 500 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 501 val FetchWidth = coreParams.FetchWidth 502 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 503 val EnableBPU = coreParams.EnableBPU 504 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 505 val EnableRAS = coreParams.EnableRAS 506 val EnableLB = coreParams.EnableLB 507 val EnableLoop = coreParams.EnableLoop 508 val EnableSC = coreParams.EnableSC 509 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 510 val HistoryLength = coreParams.HistoryLength 511 val EnableGHistDiff = coreParams.EnableGHistDiff 512 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 513 val EnableClockGate = coreParams.EnableClockGate 514 val UbtbGHRLength = coreParams.UbtbGHRLength 515 val UbtbSize = coreParams.UbtbSize 516 val EnableFauFTB = coreParams.EnableFauFTB 517 val FtbSize = coreParams.FtbSize 518 val FtbWays = coreParams.FtbWays 519 val RasSize = coreParams.RasSize 520 val RasSpecSize = coreParams.RasSpecSize 521 val RasCtrSize = coreParams.RasCtrSize 522 523 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 524 coreParams.branchPredictor(resp_in, p) 525 } 526 val numBr = coreParams.numBr 527 val TageTableInfos = coreParams.TageTableInfos 528 val TageBanks = coreParams.numBr 529 val SCNRows = coreParams.SCNRows 530 val SCCtrBits = coreParams.SCCtrBits 531 val SCHistLens = coreParams.SCHistLens 532 val SCNTables = coreParams.SCNTables 533 534 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 535 case ((n, cb), h) => (n, cb, h) 536 } 537 val ITTageTableInfos = coreParams.ITTageTableInfos 538 type FoldedHistoryInfo = Tuple2[Int, Int] 539 val foldedGHistInfos = 540 (TageTableInfos.map{ case (nRows, h, t) => 541 if (h > 0) 542 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 543 else 544 Set[FoldedHistoryInfo]() 545 }.reduce(_++_).toSet ++ 546 SCTableInfos.map{ case (nRows, _, h) => 547 if (h > 0) 548 Set((h, min(log2Ceil(nRows/TageBanks), h))) 549 else 550 Set[FoldedHistoryInfo]() 551 }.reduce(_++_).toSet ++ 552 ITTageTableInfos.map{ case (nRows, h, t) => 553 if (h > 0) 554 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 555 else 556 Set[FoldedHistoryInfo]() 557 }.reduce(_++_) ++ 558 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 559 ).toList 560 561 562 563 val CacheLineSize = coreParams.CacheLineSize 564 val CacheLineHalfWord = CacheLineSize / 16 565 val ExtHistoryLength = HistoryLength + 64 566 val ICacheECCForceError = coreParams.ICacheECCForceError 567 val IBufSize = coreParams.IBufSize 568 val IBufNBank = coreParams.IBufNBank 569 val backendParams: BackendParams = coreParams.backendParams 570 val DecodeWidth = coreParams.DecodeWidth 571 val RenameWidth = coreParams.RenameWidth 572 val CommitWidth = coreParams.CommitWidth 573 val MaxUopSize = coreParams.MaxUopSize 574 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 575 val RenameSnapshotNum = coreParams.RenameSnapshotNum 576 val FtqSize = coreParams.FtqSize 577 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 578 val IntLogicRegs = coreParams.IntLogicRegs 579 val FpLogicRegs = coreParams.FpLogicRegs 580 val VecLogicRegs = coreParams.VecLogicRegs 581 val VCONFIG_IDX = coreParams.VCONFIG_IDX 582 val IntPhyRegs = coreParams.intPreg.numEntries 583 val VfPhyRegs = coreParams.vfPreg.numEntries 584 val MaxPhyPregs = IntPhyRegs max VfPhyRegs 585 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 586 val RobSize = coreParams.RobSize 587 val RabSize = coreParams.RabSize 588 val VTypeBufferSize = coreParams.VTypeBufferSize 589 /** 590 * the minimum element length of vector elements 591 */ 592 val minVecElen: Int = coreParams.minVecElen 593 594 /** 595 * the maximum number of elements in vector register 596 */ 597 val maxElemPerVreg: Int = coreParams.maxElemPerVreg 598 599 val IntRefCounterWidth = log2Ceil(RobSize) 600 val LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth 601 val LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp 602 val LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp 603 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 604 val LoadQueueRARSize = coreParams.LoadQueueRARSize 605 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 606 val RollbackGroupSize = coreParams.RollbackGroupSize 607 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 608 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 609 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 610 val StoreQueueSize = coreParams.StoreQueueSize 611 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 612 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 613 val VlsQueueSize = coreParams.VlsQueueSize 614 val dpParams = coreParams.dpParams 615 616 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 617 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 618 619 val NumRedirect = backendParams.numRedirect 620 val BackendRedirectNum = NumRedirect + 2 //2: ldReplay + Exception 621 val FtqRedirectAheadNum = NumRedirect 622 val LoadPipelineWidth = coreParams.LoadPipelineWidth 623 val StorePipelineWidth = coreParams.StorePipelineWidth 624 val VecLoadPipelineWidth = coreParams.VecLoadPipelineWidth 625 val VecStorePipelineWidth = coreParams.VecStorePipelineWidth 626 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 627 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 628 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 629 val VecMemDispatchMaxNumber = coreParams.VecMemDispatchMaxNumber 630 val StoreBufferSize = coreParams.StoreBufferSize 631 val StoreBufferThreshold = coreParams.StoreBufferThreshold 632 val EnsbufferWidth = coreParams.EnsbufferWidth 633 val VlMergeBufferSize = coreParams.VlMergeBufferSize 634 val VsMergeBufferSize = coreParams.VsMergeBufferSize 635 val UopWritebackWidth = coreParams.UopWritebackWidth 636 val SplitBufferSize = coreParams.SplitBufferSize 637 val UncacheBufferSize = coreParams.UncacheBufferSize 638 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 639 val EnableFastForward = coreParams.EnableFastForward 640 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 641 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 642 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 643 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 644 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 645 val EnableStorePrefetchAtIssue = coreParams.EnableStorePrefetchAtIssue 646 val EnableStorePrefetchAtCommit = coreParams.EnableStorePrefetchAtCommit 647 val EnableAtCommitMissTrigger = coreParams.EnableAtCommitMissTrigger 648 val EnableStorePrefetchSMS = coreParams.EnableStorePrefetchSMS 649 val EnableStorePrefetchSPB = coreParams.EnableStorePrefetchSPB 650 val asidLen = coreParams.MMUAsidLen 651 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 652 val refillBothTlb = coreParams.refillBothTlb 653 val iwpuParam = coreParams.iwpuParameters 654 val dwpuParam = coreParams.dwpuParameters 655 val itlbParams = coreParams.itlbParameters 656 val ldtlbParams = coreParams.ldtlbParameters 657 val sttlbParams = coreParams.sttlbParameters 658 val hytlbParams = coreParams.hytlbParameters 659 val pftlbParams = coreParams.pftlbParameters 660 val btlbParams = coreParams.btlbParameters 661 val l2tlbParams = coreParams.l2tlbParameters 662 val NumPerfCounters = coreParams.NumPerfCounters 663 664 val instBytes = if (HasCExtension) 2 else 4 665 val instOffsetBits = log2Ceil(instBytes) 666 667 val icacheParameters = coreParams.icacheParameters 668 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 669 670 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 671 // for constrained LR/SC loop 672 val LRSCCycles = 64 673 // for lr storm 674 val LRSCBackOff = 8 675 676 // cache hierarchy configurations 677 val l1BusDataWidth = 256 678 679 // load violation predict 680 val ResetTimeMax2Pow = 20 //1078576 681 val ResetTimeMin2Pow = 10 //1024 682 // wait table parameters 683 val WaitTableSize = 1024 684 val MemPredPCWidth = log2Up(WaitTableSize) 685 val LWTUse2BitCounter = true 686 // store set parameters 687 val SSITSize = WaitTableSize 688 val LFSTSize = 32 689 val SSIDWidth = log2Up(LFSTSize) 690 val LFSTWidth = 4 691 val StoreSetEnable = true // LWT will be disabled if SS is enabled 692 val LFSTEnable = true 693 694 val PCntIncrStep: Int = 6 695 val numPCntHc: Int = 25 696 val numPCntPtw: Int = 19 697 698 val numCSRPCntFrontend = 8 699 val numCSRPCntCtrl = 8 700 val numCSRPCntLsu = 8 701 val numCSRPCntHc = 5 702 val printEventCoding = true 703 704 // Parameters for Sdtrig extension 705 protected val TriggerNum = 4 706 protected val TriggerChainMaxLength = 2 707} 708