History log of /XiangShan/src/main/scala/utils/ (Results 76 – 100 of 399)
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bcce877b12-Jul-2022 Yinan Xu <[email protected]>

rs: optimize timing for dispatch and wakeup (#1621)

This commit optimizes the timing of reservation stations.

* dispatched uops are latched and bypassed to s1_out

* wakeup from slowPorts are l

rs: optimize timing for dispatch and wakeup (#1621)

This commit optimizes the timing of reservation stations.

* dispatched uops are latched and bypassed to s1_out

* wakeup from slowPorts are latched and bypassed to s1_data

* rs: optimize allocation selection

Change select policy for allocation. Should avoid issuing the just
dispatched instructions in some cases.

* rs: disable load balance for load units

show more ...

0dc4893d10-Jul-2022 Yinan Xu <[email protected]>

core: optimize redirect timing (#1630)

This commit adds separated redirect registers in ExuBlock and MemBlock.
They have one cycle latency compared to redirect in CtrlBlock. This will
help reduce

core: optimize redirect timing (#1630)

This commit adds separated redirect registers in ExuBlock and MemBlock.
They have one cycle latency compared to redirect in CtrlBlock. This will
help reduce the fanout of redirect registers.

show more ...

1a9f1d7306-Jul-2022 Yinan Xu <[email protected]>

utils,perf: optimize timing (#1620)

This commit adds a pipeline for performance counters. No functional changes.

00210c3406-Jul-2022 Yinan Xu <[email protected]>

dpq: optimize read and write timing of data module (#1610)

This commit changes the data modules in Dispatch Queue. We use one-hot
indices to read and write the data array.


CircularQueuePtr.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/package.scala
fa9d712c27-Jun-2022 Yinan Xu <[email protected]>

dp2: add a pipeline for load/store (#1597)

* dp2: add a pipeline for load/store

Load/store Dispatch2 has a bad timing because it requires the fuType
to disguish the out ports. This brings timing

dp2: add a pipeline for load/store (#1597)

* dp2: add a pipeline for load/store

Load/store Dispatch2 has a bad timing because it requires the fuType
to disguish the out ports. This brings timing issues because the
instruction has to read busyTable after the port arbitration.

This commit adds a pipeline in dp2Ls, which may cause performance
degradation. Instructions are dispatched according to out, and at
the next cycle it will leave dp2.

* bump difftest trying to fix vcs

show more ...

5ef86c3825-Jun-2022 Yinan Xu <[email protected]>

freelist: optimize timing of read and writing (#1593)

This commit optimizes the timing of freelist by changing the updating
function of headPtr and tailPtr.

We maintains an one-hot representatio

freelist: optimize timing of read and writing (#1593)

This commit optimizes the timing of freelist by changing the updating
function of headPtr and tailPtr.

We maintains an one-hot representation of headPtr and further uses it to
read the free registers from the list, which should be better than the
previous implementation where headPtr is used to indexed into the queue.

The update of tailPtr and the freelist is delayed by one cycle to
optimize the timing. Because freelist allocates new registers in the
next cycle iff there are more than RenameWidth free registers in this
cycle. The freed registers in this cycle will never be used in the next
cycle. Thus, we can delay the updating of queue data to the next cycle.
We also move the update of tailPtr to the next cycle, since PopCount
takes a long timing and we move the last adder to the next cycle. Now
the adder works parallely with PopCount. That is, the updating of
tailPtr is pipelined.

show more ...

5010f3fb22-Jun-2022 Yinan Xu <[email protected]>

core: add buffers for function units across int/fp (#1590)

This commit adds a buffer after the function unit that operate across
the integer block and the floating-point block, such as f2i and i2f.

core: add buffers for function units across int/fp (#1590)

This commit adds a buffer after the function unit that operate across
the integer block and the floating-point block, such as f2i and i2f.

For example, previously the out.ready of f2i depends on whether
mul/div/csr/jump has a valid instruction out, since f2i has lower
priority than them. This ready back-propagates from the integer function
units to the floating-point function units, and finally to the
floating-point reservation stations (since f2i is fully pipelined).

We add a buffer after the function unit to break this ready
back-propagation. It incurs one more cycle of execution latency, but we
leave it not-fully-optimized for now.

Timing can be further optimized if we separates the int writeback and fp
writeback in function units. In the current version, the ready of f2i
affects the ready of f2f pipelines, which is unnecessary. This is the
future work.

show more ...

0c2f5c4a21-Jun-2022 Yinan Xu <[email protected]>

core,perf: optimize timing for some registers (#1589)

This commit adds some registers for performance counters to optimize
the timing. Pipelines are added.

d18dc7e618-Jun-2022 wakafa <[email protected]>

perfcnt: keep strict regularity of perf counter name (#1585)

* buspmu: avoid inner space in perf-cnt name

* perfcnt: judge regularity of perfname

* perfcnt: fix some irregular perfname

* bu

perfcnt: keep strict regularity of perf counter name (#1585)

* buspmu: avoid inner space in perf-cnt name

* perfcnt: judge regularity of perfname

* perfcnt: fix some irregular perfname

* bump huancun

show more ...

decb820308-Jun-2022 Lingrui98 <[email protected]>

FoldedSRAMTemplate: hold ridx when holdRead is set

8f15385a06-Jun-2022 Lemover <[email protected]>

util.sram: rm a r/w hazard mux which is not needed. bump huancun (#1571)

* bump huancun, update Chisel3, revert sram hazard enhancement

* util.sram: rm a r/w hazard mux which is not needed. bump

util.sram: rm a r/w hazard mux which is not needed. bump huancun (#1571)

* bump huancun, update Chisel3, revert sram hazard enhancement

* util.sram: rm a r/w hazard mux which is not needed. bump huancun

show more ...


/XiangShan/huancun
/XiangShan/rocket-chip
/XiangShan/src/main/scala/device/RocketDebugWrapper.scala
/XiangShan/src/main/scala/system/SoC.scala
SRAMTemplate.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/top/SimTop.scala
d0f0910425-May-2022 Steve Gou <[email protected]>

Merge pull request #1559 from OpenXiangShan/fix-folded-sram-template

sramtemplate: fix waymask in FoldedSRAMTemplate

a068fa3224-May-2022 Lingrui98 <[email protected]>

sramtemplate: fix waymask in FoldedSRAMTemplate


/XiangShan/.github/workflows/emu.yml
/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/difftest
/XiangShan/fudian
/XiangShan/huancun
/XiangShan/images/xs-arch-nanhu.svg
/XiangShan/images/xs-arch-yanqihu.svg
/XiangShan/readme.zh-cn.md
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
SRAMTemplate.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PTW.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/RAS.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ReleaseUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/test/scala/top/SimTop.scala
46f74b5706-May-2022 Haojin Tang <[email protected]>

feat: parameterize load store (#1527)

* feat: parameterize load/store pipeline, etc.

* fix: use LoadPipelineWidth rather than LoadQueueSize

* fix: parameterize `rdataPtrExtNext`

* SBuffer:

feat: parameterize load store (#1527)

* feat: parameterize load/store pipeline, etc.

* fix: use LoadPipelineWidth rather than LoadQueueSize

* fix: parameterize `rdataPtrExtNext`

* SBuffer: fix idx update logic

* atomic: parameterize atomic logic in `MemBlock`

* StoreQueue: update allow enque requirement

* feat: support one load/store pipeline

* feat: parameterize `EnsbufferWidth`

* chore: resharp codes for better generated name

show more ...


/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/nightly.yml
/XiangShan/.gitignore
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/AXI4IntrGenerator.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Generator.scala
/XiangShan/src/main/scala/top/Top.scala
BitUtils.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Rs.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/DatamoduleResultBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/top/SimTop.scala
9658ce5025-Mar-2022 LinJiawei <[email protected]>

Bump chisel to 3.5.0


/XiangShan/build.sc
MIMOQueue.scala
ParallelMux.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/PayloadArray.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala
/XiangShan/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/DatamoduleResultBuffer.scala
7008379430-Mar-2022 Lemover <[email protected]>

sram-tlb: change SRAMTemplate & when tlb refill, just resp a miss/fast_miss (#1504)

* bump huancun

* sram: fix sram, keep rdata when w.valid

* tlb: when refill, just return miss at next cycle,

sram-tlb: change SRAMTemplate & when tlb refill, just resp a miss/fast_miss (#1504)

* bump huancun

* sram: fix sram, keep rdata when w.valid

* tlb: when refill, just return miss at next cycle, rm unused assert

show more ...


/XiangShan/.github/workflows/emu.yml
/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/difftest
/XiangShan/fudian
/XiangShan/huancun
/XiangShan/images/xs-arch-nanhu.svg
/XiangShan/images/xs-arch-yanqihu.svg
/XiangShan/readme.zh-cn.md
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
SRAMTemplate.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PTW.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/RAS.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ReleaseUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/test/scala/top/SimTop.scala
25cb35b628-Jan-2022 Jiawei Lin <[email protected]>

Adjusted reset signals (#1441)

* Adjusted reset signals

* Support reset tree


/XiangShan/.github/workflows/emu.yml
/XiangShan/huancun
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
ResetGen.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/RAS.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ReleaseUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
4813e06007-Jan-2022 Lingrui98 <[email protected]>

tage: improve performance and reduce area

* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch pre

tage: improve performance and reduce area

* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch predictor components
in order to remove casting operation in composer

show more ...


/XiangShan/huancun
SRAMTemplate.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/MetaArray.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Bim.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/RAS.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala
5cf832d931-Dec-2021 Lingrui98 <[email protected]>

Merge remote-tracking branch 'origin/master' into bpu-timing


/XiangShan/huancun
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
CircularQueuePtr.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/MetaArray.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheProbeUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
e9ae4a3b27-Dec-2021 Yinan Xu <[email protected]>

queuePtr: set isAfter when different flags and same value (#1396)

For 0:x and 1:x, 1:x should be after 0:x.


/XiangShan/.github/workflows/emu.yml
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/scripts/xiangshan.py
CircularQueuePtr.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
cb4b23c023-Dec-2021 Lingrui98 <[email protected]>

Merge remote-tracking branch 'origin/master' into bpu-timing


/XiangShan/.github/workflows/emu.yml
/XiangShan/README.md
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/ready-to-run
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/RocketDebugWrapper.scala
/XiangShan/src/main/scala/top/Configs.scala
BitUtils.scala
Trigger.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/PMParameters.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Rs.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Bim.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/RAS.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
67c26c3421-Dec-2021 William Wang <[email protected]>

sbuffer: optimize sbuffer enqueue timing (#1379)

This commit removed PriorityEncoder in sbuffer enq path. It should improve sbuffer enqueue timing.


/XiangShan/README.md
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/ready-to-run
/XiangShan/src/main/scala/device/RocketDebugWrapper.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
BitUtils.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/PMParameters.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Rs.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PTW.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
c49b0e7f14-Dec-2021 Lingrui98 <[email protected]>

Merge remote-tracking branch 'origin/change-fallThrough' into ubtb-refactor


/XiangShan/.gitmodules
/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/build.sc
/XiangShan/difftest
/XiangShan/fudian
/XiangShan/huancun
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/AXI4IntrGenerator.scala
/XiangShan/src/main/scala/device/TLPMA/TLPMA.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
BinaryArbiterNode.scala
Hold.scala
PerfCounterUtils.scala
TLClientsMerger.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/PMParameters.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Rs.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CryptoUtils.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PTW.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheProbeUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ReleaseUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/top/SimTop.scala
b30c10d614-Dec-2021 Lingrui98 <[email protected]>

bpu: timing optimizations

* use parallel mux to select provider and altprovider for TAGE and ITTAGE
* reduce logics on SC prediction
* calculate higher bits of targets at stage 1 for ftb
* reduce lo

bpu: timing optimizations

* use parallel mux to select provider and altprovider for TAGE and ITTAGE
* reduce logics on SC prediction
* calculate higher bits of targets at stage 1 for ftb
* reduce logics for RAS and ITTAGE prediction assignment

show more ...

068bf97810-Dec-2021 Li Qianruo <[email protected]>

Merge branch 'master' into trigger


/XiangShan/difftest
/XiangShan/fudian
/XiangShan/huancun
/XiangShan/ready-to-run
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/AXI4IntrGenerator.scala
/XiangShan/src/main/scala/device/TLPMA/TLPMA.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
BinaryArbiterNode.scala
PerfCounterUtils.scala
TLClientsMerger.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/PMParameters.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Rs.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CryptoUtils.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PTW.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheProbeUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ReleaseUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/top/SimTop.scala

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