1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, MicroBTB, RAS, Tage, ITTage, Tage_SC} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableUBTB: Boolean = true, 64 HistoryLength: Int = 512, 65 PathHistoryLength: Int = 16, 66 BtbSize: Int = 2048, 67 JbtacSize: Int = 1024, 68 JbtacBanks: Int = 8, 69 RasSize: Int = 32, 70 CacheLineSize: Int = 512, 71 UBtbWays: Int = 16, 72 BtbWays: Int = 2, 73 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 74 // Sets Hist Tag 75 Seq(( 128*8, 2, 9), 76 ( 128*8, 8, 9), 77 ( 128*8, 12, 9), 78 ( 128*8, 13, 9), 79 ( 128*8, 28, 9), 80 ( 128*8, 54, 9), 81 ( 128*8, 119, 9), 82 ( 128*8, 256, 9)), 83 TageBanks: Int = 2, 84 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 85 // Sets Hist Tag 86 Seq(( 512, 0, 0), 87 ( 256, 4, 8), 88 ( 256, 8, 8), 89 ( 512, 12, 8), 90 ( 512, 16, 8), 91 ( 512, 32, 8)), 92 SCNRows: Int = 512, 93 SCNTables: Int = 4, 94 SCCtrBits: Int = 6, 95 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 96 numBr: Int = 2, 97 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 98 ((resp_in: BranchPredictionResp, p: Parameters) => { 99 // val loop = Module(new LoopPredictor) 100 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 101 // else Module(new Tage) } 102 // else { Module(new FakeTage) }) 103 val ftb = Module(new FTB()(p)) 104 val ubtb = Module(new MicroBTB()(p)) 105 val bim = Module(new BIM()(p)) 106 val tage = Module(new Tage_SC()(p)) 107 val ras = Module(new RAS()(p)) 108 val ittage = Module(new ITTage()(p)) 109 // val tage = Module(new Tage()(p)) 110 // val fake = Module(new FakePredictor()(p)) 111 112 // val preds = Seq(loop, tage, btb, ubtb, bim) 113 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 114 preds.map(_.io := DontCare) 115 116 // ubtb.io.resp_in(0) := resp_in 117 // bim.io.resp_in(0) := ubtb.io.resp 118 // btb.io.resp_in(0) := bim.io.resp 119 // tage.io.resp_in(0) := btb.io.resp 120 // loop.io.resp_in(0) := tage.io.resp 121 bim.io.in.bits.resp_in(0) := resp_in 122 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 123 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 124 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 125 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 126 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 127 128 (preds, ras.io.out.resp) 129 }), 130 IBufSize: Int = 48, 131 DecodeWidth: Int = 6, 132 RenameWidth: Int = 6, 133 CommitWidth: Int = 6, 134 FtqSize: Int = 64, 135 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 136 IssQueSize: Int = 16, 137 NRPhyRegs: Int = 192, 138 LoadQueueSize: Int = 80, 139 StoreQueueSize: Int = 64, 140 RobSize: Int = 256, 141 dpParams: DispatchParameters = DispatchParameters( 142 IntDqSize = 16, 143 FpDqSize = 16, 144 LsDqSize = 16, 145 IntDqDeqWidth = 4, 146 FpDqDeqWidth = 4, 147 LsDqDeqWidth = 4 148 ), 149 exuParameters: ExuParameters = ExuParameters( 150 JmpCnt = 1, 151 AluCnt = 4, 152 MulCnt = 0, 153 MduCnt = 2, 154 FmacCnt = 4, 155 FmiscCnt = 2, 156 FmiscDivSqrtCnt = 0, 157 LduCnt = 2, 158 StuCnt = 2 159 ), 160 LoadPipelineWidth: Int = 2, 161 StorePipelineWidth: Int = 2, 162 StoreBufferSize: Int = 16, 163 StoreBufferThreshold: Int = 7, 164 EnableLoadToLoadForward: Boolean = false, 165 EnableFastForward: Boolean = false, 166 EnableLdVioCheckAfterReset: Boolean = true, 167 RefillSize: Int = 512, 168 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 169 itlbParameters: TLBParameters = TLBParameters( 170 name = "itlb", 171 fetchi = true, 172 useDmode = false, 173 sameCycle = false, 174 missSameCycle = true, 175 normalNWays = 32, 176 normalReplacer = Some("plru"), 177 superNWays = 4, 178 superReplacer = Some("plru"), 179 shouldBlock = true 180 ), 181 ldtlbParameters: TLBParameters = TLBParameters( 182 name = "ldtlb", 183 normalNSets = 128, 184 normalNWays = 1, 185 normalAssociative = "sa", 186 normalReplacer = Some("setplru"), 187 superNWays = 8, 188 normalAsVictim = true, 189 outReplace = true, 190 saveLevel = true 191 ), 192 sttlbParameters: TLBParameters = TLBParameters( 193 name = "sttlb", 194 normalNSets = 128, 195 normalNWays = 1, 196 normalAssociative = "sa", 197 normalReplacer = Some("setplru"), 198 superNWays = 8, 199 normalAsVictim = true, 200 outReplace = true, 201 saveLevel = true 202 ), 203 refillBothTlb: Boolean = false, 204 btlbParameters: TLBParameters = TLBParameters( 205 name = "btlb", 206 normalNSets = 1, 207 normalNWays = 64, 208 superNWays = 4, 209 ), 210 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 211 NumPerfCounters: Int = 16, 212 icacheParameters: ICacheParameters = ICacheParameters( 213 tagECC = Some("parity"), 214 dataECC = Some("parity"), 215 replacer = Some("setplru"), 216 nMissEntries = 2, 217 nReleaseEntries = 2 218 ), 219 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 220 tagECC = Some("secded"), 221 dataECC = Some("secded"), 222 replacer = Some("setplru"), 223 nMissEntries = 16, 224 nProbeEntries = 8, 225 nReleaseEntries = 18 226 )), 227 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 228 name = "l2", 229 level = 2, 230 ways = 8, 231 sets = 1024, // default 512KB L2 232 prefetch = Some(huancun.prefetch.BOPParameters()) 233 )), 234 L2NBanks: Int = 1, 235 usePTWRepeater: Boolean = false, 236 softPTW: Boolean = false // dpi-c debug only 237){ 238 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 239 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 240 241 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 242 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 243 244 val fpExuConfigs = 245 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 246 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 247 248 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 249} 250 251case object DebugOptionsKey extends Field[DebugOptions] 252 253case class DebugOptions 254( 255 FPGAPlatform: Boolean = false, 256 EnableDifftest: Boolean = false, 257 AlwaysBasicDiff: Boolean = true, 258 EnableDebug: Boolean = false, 259 EnablePerfDebug: Boolean = true, 260 UseDRAMSim: Boolean = false 261) 262 263trait HasXSParameter { 264 265 implicit val p: Parameters 266 267 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 268 269 val coreParams = p(XSCoreParamsKey) 270 val env = p(DebugOptionsKey) 271 272 val XLEN = coreParams.XLEN 273 val minFLen = 32 274 val fLen = 64 275 def xLen = XLEN 276 277 val HasMExtension = coreParams.HasMExtension 278 val HasCExtension = coreParams.HasCExtension 279 val HasDiv = coreParams.HasDiv 280 val HasIcache = coreParams.HasICache 281 val HasDcache = coreParams.HasDCache 282 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 283 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 284 val AsidLength = coreParams.AsidLength 285 val AddrBytes = AddrBits / 8 // unused 286 val DataBits = XLEN 287 val DataBytes = DataBits / 8 288 val HasFPU = coreParams.HasFPU 289 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 290 val FetchWidth = coreParams.FetchWidth 291 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 292 val EnableBPU = coreParams.EnableBPU 293 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 294 val EnableRAS = coreParams.EnableRAS 295 val EnableLB = coreParams.EnableLB 296 val EnableLoop = coreParams.EnableLoop 297 val EnableSC = coreParams.EnableSC 298 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 299 val HistoryLength = coreParams.HistoryLength 300 val PathHistoryLength = coreParams.PathHistoryLength 301 val BtbSize = coreParams.BtbSize 302 // val BtbWays = 4 303 val BtbBanks = PredictWidth 304 // val BtbSets = BtbSize / BtbWays 305 val JbtacSize = coreParams.JbtacSize 306 val JbtacBanks = coreParams.JbtacBanks 307 val RasSize = coreParams.RasSize 308 309 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 310 coreParams.branchPredictor(resp_in, p) 311 } 312 val numBr = coreParams.numBr 313 val TageTableInfos = coreParams.TageTableInfos 314 315 316 val BankTageTableInfos = (0 until numBr).map(i => 317 TageTableInfos.map{ case (s, h, t) => (s/(1 << i), h, t) } 318 ) 319 val TageBanks = coreParams.TageBanks 320 val SCNRows = coreParams.SCNRows 321 val SCCtrBits = coreParams.SCCtrBits 322 val BankSCHistLens = Seq.fill(numBr)(coreParams.SCHistLens) 323 val BankSCNTables = Seq.fill(numBr)(coreParams.SCNTables) 324 325 val BankSCTableInfos = (BankSCNTables zip BankSCHistLens).map { 326 case (ntable, histlens) => 327 Seq.fill(ntable)((SCNRows, SCCtrBits)) zip histlens map {case ((n, cb), h) => (n, cb, h)} 328 } 329 val ITTageTableInfos = coreParams.ITTageTableInfos 330 type FoldedHistoryInfo = Tuple2[Int, Int] 331 val foldedGHistInfos = 332 (BankTageTableInfos.flatMap(_.map{ case (nRows, h, t) => 333 if (h > 0) 334 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 335 else 336 Set[FoldedHistoryInfo]() 337 }.reduce(_++_)).toSet ++ 338 BankSCTableInfos.flatMap(_.map{ case (nRows, _, h) => 339 if (h > 0) 340 Set((h, min(log2Ceil(nRows/TageBanks), h))) 341 else 342 Set[FoldedHistoryInfo]() 343 }.reduce(_++_)).toSet ++ 344 ITTageTableInfos.map{ case (nRows, h, t) => 345 if (h > 0) 346 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 347 else 348 Set[FoldedHistoryInfo]() 349 }.reduce(_++_)).toList 350 351 val CacheLineSize = coreParams.CacheLineSize 352 val CacheLineHalfWord = CacheLineSize / 16 353 val ExtHistoryLength = HistoryLength + 64 354 val UBtbWays = coreParams.UBtbWays 355 val BtbWays = coreParams.BtbWays 356 val IBufSize = coreParams.IBufSize 357 val DecodeWidth = coreParams.DecodeWidth 358 val RenameWidth = coreParams.RenameWidth 359 val CommitWidth = coreParams.CommitWidth 360 val FtqSize = coreParams.FtqSize 361 val IssQueSize = coreParams.IssQueSize 362 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 363 val NRPhyRegs = coreParams.NRPhyRegs 364 val PhyRegIdxWidth = log2Up(NRPhyRegs) 365 val RobSize = coreParams.RobSize 366 val IntRefCounterWidth = log2Ceil(RobSize) 367 val LoadQueueSize = coreParams.LoadQueueSize 368 val StoreQueueSize = coreParams.StoreQueueSize 369 val dpParams = coreParams.dpParams 370 val exuParameters = coreParams.exuParameters 371 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 372 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 373 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 374 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 375 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 376 val LoadPipelineWidth = coreParams.LoadPipelineWidth 377 val StorePipelineWidth = coreParams.StorePipelineWidth 378 val StoreBufferSize = coreParams.StoreBufferSize 379 val StoreBufferThreshold = coreParams.StoreBufferThreshold 380 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 381 val EnableFastForward = coreParams.EnableFastForward 382 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 383 val RefillSize = coreParams.RefillSize 384 val asidLen = coreParams.MMUAsidLen 385 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 386 val refillBothTlb = coreParams.refillBothTlb 387 val itlbParams = coreParams.itlbParameters 388 val ldtlbParams = coreParams.ldtlbParameters 389 val sttlbParams = coreParams.sttlbParameters 390 val btlbParams = coreParams.btlbParameters 391 val l2tlbParams = coreParams.l2tlbParameters 392 val NumPerfCounters = coreParams.NumPerfCounters 393 394 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 395 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 396 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 397 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 398 399 val instBytes = if (HasCExtension) 2 else 4 400 val instOffsetBits = log2Ceil(instBytes) 401 402 val icacheParameters = coreParams.icacheParameters 403 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 404 405 val LRSCCycles = 100 406 407 // cache hierarchy configurations 408 val l1BusDataWidth = 256 409 410 // load violation predict 411 val ResetTimeMax2Pow = 20 //1078576 412 val ResetTimeMin2Pow = 10 //1024 413 // wait table parameters 414 val WaitTableSize = 1024 415 val MemPredPCWidth = log2Up(WaitTableSize) 416 val LWTUse2BitCounter = true 417 // store set parameters 418 val SSITSize = WaitTableSize 419 val LFSTSize = 32 420 val SSIDWidth = log2Up(LFSTSize) 421 val LFSTWidth = 4 422 val StoreSetEnable = true // LWT will be disabled if SS is enabled 423 424 val loadExuConfigs = coreParams.loadExuConfigs 425 val storeExuConfigs = coreParams.storeExuConfigs 426 427 val intExuConfigs = coreParams.intExuConfigs 428 429 val fpExuConfigs = coreParams.fpExuConfigs 430 431 val exuConfigs = coreParams.exuConfigs 432 433 val PCntIncrStep: Int = 6 434 val numPCntHc: Int = 25 435 val numPCntPtw: Int = 19 436 437 val numCSRPCntFrontend = 8 438 val numCSRPCntCtrl = 8 439 val numCSRPCntLsu = 8 440 val numCSRPCntHc = 5 441} 442