1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.ExceptionNO._ 22import xiangshan.backend.fu._ 23import xiangshan.backend.fu.fpu._ 24import xiangshan.backend.exu._ 25import xiangshan.backend.Std 26 27package object xiangshan { 28 object SrcType { 29 def reg = "b00".U 30 def pc = "b01".U 31 def imm = "b01".U 32 def fp = "b10".U 33 34 def DC = imm // Don't Care 35 36 def isReg(srcType: UInt) = srcType===reg 37 def isPc(srcType: UInt) = srcType===pc 38 def isImm(srcType: UInt) = srcType===imm 39 def isFp(srcType: UInt) = srcType(1) 40 def isPcOrImm(srcType: UInt) = srcType(0) 41 def isRegOrFp(srcType: UInt) = !srcType(0) 42 def regIsFp(srcType: UInt) = srcType(1) 43 44 def apply() = UInt(2.W) 45 } 46 47 object SrcState { 48 def busy = "b0".U 49 def rdy = "b1".U 50 // def specRdy = "b10".U // speculative ready, for future use 51 def apply() = UInt(1.W) 52 } 53 54 object FuType { 55 def jmp = "b0000".U 56 def i2f = "b0001".U 57 def csr = "b0010".U 58 def alu = "b0110".U 59 def mul = "b0100".U 60 def div = "b0101".U 61 def fence = "b0011".U 62 def bku = "b0111".U 63 64 def fmac = "b1000".U 65 def fmisc = "b1011".U 66 def fDivSqrt = "b1010".U 67 68 def ldu = "b1100".U 69 def stu = "b1101".U 70 def mou = "b1111".U // for amo, lr, sc, fence 71 72 def num = 14 73 74 def apply() = UInt(log2Up(num).W) 75 76 def isIntExu(fuType: UInt) = !fuType(3) 77 def isJumpExu(fuType: UInt) = fuType === jmp 78 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 79 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 80 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 81 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 82 def isAMO(fuType: UInt) = fuType(1) 83 def isFence(fuType: UInt) = fuType === fence 84 def isSvinvalBegin(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && !flush 85 def isSvinval(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.sfence && !flush 86 def isSvinvalEnd(fuType: UInt, func: UInt, flush: Bool) = isFence(fuType) && func === FenceOpType.nofence && flush 87 88 89 def jmpCanAccept(fuType: UInt) = !fuType(2) 90 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 91 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 92 93 def fmacCanAccept(fuType: UInt) = !fuType(1) 94 def fmiscCanAccept(fuType: UInt) = fuType(1) 95 96 def loadCanAccept(fuType: UInt) = !fuType(0) 97 def storeCanAccept(fuType: UInt) = fuType(0) 98 99 def storeIsAMO(fuType: UInt) = fuType(1) 100 101 val functionNameMap = Map( 102 jmp.litValue() -> "jmp", 103 i2f.litValue() -> "int_to_float", 104 csr.litValue() -> "csr", 105 alu.litValue() -> "alu", 106 mul.litValue() -> "mul", 107 div.litValue() -> "div", 108 fence.litValue() -> "fence", 109 bku.litValue() -> "bku", 110 fmac.litValue() -> "fmac", 111 fmisc.litValue() -> "fmisc", 112 fDivSqrt.litValue() -> "fdiv_fsqrt", 113 ldu.litValue() -> "load", 114 stu.litValue() -> "store", 115 mou.litValue() -> "mou" 116 ) 117 } 118 119 object FuOpType { 120 def apply() = UInt(7.W) 121 def X = BitPat("b???????") 122 } 123 124 object CommitType { 125 def NORMAL = "b000".U // int/fp 126 def BRANCH = "b001".U // branch 127 def LOAD = "b010".U // load 128 def STORE = "b011".U // store 129 130 def apply() = UInt(3.W) 131 def isFused(commitType: UInt): Bool = commitType(2) 132 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 133 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 134 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 135 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 136 } 137 138 object RedirectLevel { 139 def flushAfter = "b0".U 140 def flush = "b1".U 141 142 def apply() = UInt(1.W) 143 // def isUnconditional(level: UInt) = level(1) 144 def flushItself(level: UInt) = level(0) 145 // def isException(level: UInt) = level(1) && level(0) 146 } 147 148 object ExceptionVec { 149 def apply() = Vec(16, Bool()) 150 } 151 152 object PMAMode { 153 def R = "b1".U << 0 //readable 154 def W = "b1".U << 1 //writeable 155 def X = "b1".U << 2 //executable 156 def I = "b1".U << 3 //cacheable: icache 157 def D = "b1".U << 4 //cacheable: dcache 158 def S = "b1".U << 5 //enable speculative access 159 def A = "b1".U << 6 //enable atomic operation, A imply R & W 160 def C = "b1".U << 7 //if it is cacheable is configable 161 def Reserved = "b0".U 162 163 def apply() = UInt(7.W) 164 165 def read(mode: UInt) = mode(0) 166 def write(mode: UInt) = mode(1) 167 def execute(mode: UInt) = mode(2) 168 def icache(mode: UInt) = mode(3) 169 def dcache(mode: UInt) = mode(4) 170 def speculate(mode: UInt) = mode(5) 171 def atomic(mode: UInt) = mode(6) 172 def configable_cache(mode: UInt) = mode(7) 173 174 def strToMode(s: String) = { 175 var result = 0.U(8.W) 176 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 177 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 178 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 179 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 180 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 181 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 182 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 183 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 184 result 185 } 186 } 187 188 189 object CSROpType { 190 def jmp = "b000".U 191 def wrt = "b001".U 192 def set = "b010".U 193 def clr = "b011".U 194 def wfi = "b100".U 195 def wrti = "b101".U 196 def seti = "b110".U 197 def clri = "b111".U 198 def needAccess(op: UInt): Bool = op(1, 0) =/= 0.U 199 } 200 201 // jump 202 object JumpOpType { 203 def jal = "b00".U 204 def jalr = "b01".U 205 def auipc = "b10".U 206// def call = "b11_011".U 207// def ret = "b11_100".U 208 def jumpOpisJalr(op: UInt) = op(0) 209 def jumpOpisAuipc(op: UInt) = op(1) 210 } 211 212 object FenceOpType { 213 def fence = "b10000".U 214 def sfence = "b10001".U 215 def fencei = "b10010".U 216 def nofence= "b00000".U 217 } 218 219 object ALUOpType { 220 // shift optype 221 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 222 def sll = "b000_0001".U // sll: src1 << src2 223 224 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 225 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 226 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 227 228 def srl = "b000_0101".U // srl: src1 >> src2 229 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 230 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 231 232 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 233 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 234 235 // RV64 32bit optype 236 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 237 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 238 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 239 240 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 241 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 242 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 243 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 244 245 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 246 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 247 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 248 def rolw = "b001_1100".U 249 def rorw = "b001_1101".U 250 251 // ADD-op 252 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 253 def add = "b010_0001".U // add: src1 + src2 254 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 255 256 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 257 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 258 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 259 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 260 261 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 262 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 263 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 264 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 265 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 266 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 267 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 268 269 // SUB-op: src1 - src2 270 def sub = "b011_0000".U 271 def sltu = "b011_0001".U 272 def slt = "b011_0010".U 273 def maxu = "b011_0100".U 274 def minu = "b011_0101".U 275 def max = "b011_0110".U 276 def min = "b011_0111".U 277 278 // branch 279 def beq = "b111_0000".U 280 def bne = "b111_0010".U 281 def blt = "b111_1000".U 282 def bge = "b111_1010".U 283 def bltu = "b111_1100".U 284 def bgeu = "b111_1110".U 285 286 // misc optype 287 def and = "b100_0000".U 288 def andn = "b100_0001".U 289 def or = "b100_0010".U 290 def orn = "b100_0011".U 291 def xor = "b100_0100".U 292 def xnor = "b100_0101".U 293 def orcb = "b100_0110".U 294 295 def sextb = "b100_1000".U 296 def packh = "b100_1001".U 297 def sexth = "b100_1010".U 298 def packw = "b100_1011".U 299 300 def revb = "b101_0000".U 301 def rev8 = "b101_0001".U 302 def pack = "b101_0010".U 303 def orh48 = "b101_0011".U 304 305 def szewl1 = "b101_1000".U 306 def szewl2 = "b101_1001".U 307 def szewl3 = "b101_1010".U 308 def byte2 = "b101_1011".U 309 310 def andlsb = "b110_0000".U 311 def andzexth = "b110_0001".U 312 def orlsb = "b110_0010".U 313 def orzexth = "b110_0011".U 314 def xorlsb = "b110_0100".U 315 def xorzexth = "b110_0101".U 316 def orcblsb = "b110_0110".U 317 def orcbzexth = "b110_0111".U 318 319 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 320 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 321 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 322 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 323 def isBranch(func: UInt) = func(6, 4) === "b111".U 324 def getBranchType(func: UInt) = func(3, 2) 325 def isBranchInvert(func: UInt) = func(1) 326 327 def apply() = UInt(7.W) 328 } 329 330 object MDUOpType { 331 // mul 332 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 333 def mul = "b00000".U 334 def mulh = "b00001".U 335 def mulhsu = "b00010".U 336 def mulhu = "b00011".U 337 def mulw = "b00100".U 338 339 def mulw7 = "b01100".U 340 341 // div 342 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 343 def div = "b10000".U 344 def divu = "b10010".U 345 def rem = "b10001".U 346 def remu = "b10011".U 347 348 def divw = "b10100".U 349 def divuw = "b10110".U 350 def remw = "b10101".U 351 def remuw = "b10111".U 352 353 def isMul(op: UInt) = !op(4) 354 def isDiv(op: UInt) = op(4) 355 356 def isDivSign(op: UInt) = isDiv(op) && !op(1) 357 def isW(op: UInt) = op(2) 358 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 359 def getMulOp(op: UInt) = op(1, 0) 360 } 361 362 object LSUOpType { 363 // load pipeline 364 365 // normal load 366 // Note: bit(1, 0) are size, DO NOT CHANGE 367 // bit encoding: | load 0 | is unsigned(1bit) | size(2bit) | 368 def lb = "b0000".U 369 def lh = "b0001".U 370 def lw = "b0010".U 371 def ld = "b0011".U 372 def lbu = "b0100".U 373 def lhu = "b0101".U 374 def lwu = "b0110".U 375 376 // Zicbop software prefetch 377 // bit encoding: | prefetch 1 | 0 | prefetch type (2bit) | 378 def prefetch_i = "b1000".U // TODO 379 def prefetch_r = "b1001".U 380 def prefetch_w = "b1010".U 381 382 def isPrefetch(op: UInt): Bool = op(3) 383 384 // store pipeline 385 // normal store 386 // bit encoding: | store 00 | size(2bit) | 387 def sb = "b0000".U 388 def sh = "b0001".U 389 def sw = "b0010".U 390 def sd = "b0011".U 391 392 // l1 cache op 393 // bit encoding: | cbo_zero 01 | size(2bit) 11 | 394 def cbo_zero = "b0111".U 395 396 // llc op 397 // bit encoding: | prefetch 11 | suboptype(2bit) | 398 def cbo_clean = "b1100".U 399 def cbo_flush = "b1101".U 400 def cbo_inval = "b1110".U 401 402 def isCbo(op: UInt): Bool = op(3, 2) === "b11".U 403 404 // atomics 405 // bit(1, 0) are size 406 // since atomics use a different fu type 407 // so we can safely reuse other load/store's encodings 408 // bit encoding: | optype(4bit) | size (2bit) | 409 def lr_w = "b000010".U 410 def sc_w = "b000110".U 411 def amoswap_w = "b001010".U 412 def amoadd_w = "b001110".U 413 def amoxor_w = "b010010".U 414 def amoand_w = "b010110".U 415 def amoor_w = "b011010".U 416 def amomin_w = "b011110".U 417 def amomax_w = "b100010".U 418 def amominu_w = "b100110".U 419 def amomaxu_w = "b101010".U 420 421 def lr_d = "b000011".U 422 def sc_d = "b000111".U 423 def amoswap_d = "b001011".U 424 def amoadd_d = "b001111".U 425 def amoxor_d = "b010011".U 426 def amoand_d = "b010111".U 427 def amoor_d = "b011011".U 428 def amomin_d = "b011111".U 429 def amomax_d = "b100011".U 430 def amominu_d = "b100111".U 431 def amomaxu_d = "b101011".U 432 433 def size(op: UInt) = op(1,0) 434 } 435 436 object BKUOpType { 437 438 def clmul = "b000000".U 439 def clmulh = "b000001".U 440 def clmulr = "b000010".U 441 def xpermn = "b000100".U 442 def xpermb = "b000101".U 443 444 def clz = "b001000".U 445 def clzw = "b001001".U 446 def ctz = "b001010".U 447 def ctzw = "b001011".U 448 def cpop = "b001100".U 449 def cpopw = "b001101".U 450 451 // 01xxxx is reserve 452 def aes64es = "b100000".U 453 def aes64esm = "b100001".U 454 def aes64ds = "b100010".U 455 def aes64dsm = "b100011".U 456 def aes64im = "b100100".U 457 def aes64ks1i = "b100101".U 458 def aes64ks2 = "b100110".U 459 460 // merge to two instruction sm4ks & sm4ed 461 def sm4ed0 = "b101000".U 462 def sm4ed1 = "b101001".U 463 def sm4ed2 = "b101010".U 464 def sm4ed3 = "b101011".U 465 def sm4ks0 = "b101100".U 466 def sm4ks1 = "b101101".U 467 def sm4ks2 = "b101110".U 468 def sm4ks3 = "b101111".U 469 470 def sha256sum0 = "b110000".U 471 def sha256sum1 = "b110001".U 472 def sha256sig0 = "b110010".U 473 def sha256sig1 = "b110011".U 474 def sha512sum0 = "b110100".U 475 def sha512sum1 = "b110101".U 476 def sha512sig0 = "b110110".U 477 def sha512sig1 = "b110111".U 478 479 def sm3p0 = "b111000".U 480 def sm3p1 = "b111001".U 481 } 482 483 object BTBtype { 484 def B = "b00".U // branch 485 def J = "b01".U // jump 486 def I = "b10".U // indirect 487 def R = "b11".U // return 488 489 def apply() = UInt(2.W) 490 } 491 492 object SelImm { 493 def IMM_X = "b0111".U 494 def IMM_S = "b0000".U 495 def IMM_SB = "b0001".U 496 def IMM_U = "b0010".U 497 def IMM_UJ = "b0011".U 498 def IMM_I = "b0100".U 499 def IMM_Z = "b0101".U 500 def INVALID_INSTR = "b0110".U 501 def IMM_B6 = "b1000".U 502 503 def apply() = UInt(4.W) 504 } 505 506 object ExceptionNO { 507 def instrAddrMisaligned = 0 508 def instrAccessFault = 1 509 def illegalInstr = 2 510 def breakPoint = 3 511 def loadAddrMisaligned = 4 512 def loadAccessFault = 5 513 def storeAddrMisaligned = 6 514 def storeAccessFault = 7 515 def ecallU = 8 516 def ecallS = 9 517 def ecallM = 11 518 def instrPageFault = 12 519 def loadPageFault = 13 520 // def singleStep = 14 521 def storePageFault = 15 522 def priorities = Seq( 523 breakPoint, // TODO: different BP has different priority 524 instrPageFault, 525 instrAccessFault, 526 illegalInstr, 527 instrAddrMisaligned, 528 ecallM, ecallS, ecallU, 529 storePageFault, 530 loadPageFault, 531 storeAccessFault, 532 loadAccessFault, 533 storeAddrMisaligned, 534 loadAddrMisaligned 535 ) 536 def all = priorities.distinct.sorted 537 def frontendSet = Seq( 538 instrAddrMisaligned, 539 instrAccessFault, 540 illegalInstr, 541 instrPageFault 542 ) 543 def partialSelect(vec: Vec[Bool], select: Seq[Int]): Vec[Bool] = { 544 val new_vec = Wire(ExceptionVec()) 545 new_vec.foreach(_ := false.B) 546 select.foreach(i => new_vec(i) := vec(i)) 547 new_vec 548 } 549 def selectFrontend(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, frontendSet) 550 def selectAll(vec: Vec[Bool]): Vec[Bool] = partialSelect(vec, ExceptionNO.all) 551 def selectByFu(vec:Vec[Bool], fuConfig: FuConfig): Vec[Bool] = 552 partialSelect(vec, fuConfig.exceptionOut) 553 def selectByExu(vec:Vec[Bool], exuConfig: ExuConfig): Vec[Bool] = 554 partialSelect(vec, exuConfig.exceptionOut) 555 def selectByExu(vec:Vec[Bool], exuConfigs: Seq[ExuConfig]): Vec[Bool] = 556 partialSelect(vec, exuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted) 557 } 558 559 def dividerGen(p: Parameters) = new SRT16Divider(p(XLen))(p) 560 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 561 def aluGen(p: Parameters) = new Alu()(p) 562 def bkuGen(p: Parameters) = new Bku()(p) 563 def jmpGen(p: Parameters) = new Jump()(p) 564 def fenceGen(p: Parameters) = new Fence()(p) 565 def csrGen(p: Parameters) = new CSR()(p) 566 def i2fGen(p: Parameters) = new IntToFP()(p) 567 def fmacGen(p: Parameters) = new FMA()(p) 568 def f2iGen(p: Parameters) = new FPToInt()(p) 569 def f2fGen(p: Parameters) = new FPToFP()(p) 570 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 571 def stdGen(p: Parameters) = new Std()(p) 572 def mouDataGen(p: Parameters) = new Std()(p) 573 574 def f2iSel(uop: MicroOp): Bool = { 575 uop.ctrl.rfWen 576 } 577 578 def i2fSel(uop: MicroOp): Bool = { 579 uop.ctrl.fpu.fromInt 580 } 581 582 def f2fSel(uop: MicroOp): Bool = { 583 val ctrl = uop.ctrl.fpu 584 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 585 } 586 587 def fdivSqrtSel(uop: MicroOp): Bool = { 588 val ctrl = uop.ctrl.fpu 589 ctrl.div || ctrl.sqrt 590 } 591 592 val aluCfg = FuConfig( 593 name = "alu", 594 fuGen = aluGen, 595 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 596 fuType = FuType.alu, 597 numIntSrc = 2, 598 numFpSrc = 0, 599 writeIntRf = true, 600 writeFpRf = false, 601 hasRedirect = true, 602 ) 603 604 val jmpCfg = FuConfig( 605 name = "jmp", 606 fuGen = jmpGen, 607 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 608 fuType = FuType.jmp, 609 numIntSrc = 1, 610 numFpSrc = 0, 611 writeIntRf = true, 612 writeFpRf = false, 613 hasRedirect = true, 614 ) 615 616 val fenceCfg = FuConfig( 617 name = "fence", 618 fuGen = fenceGen, 619 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 620 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, 621 latency = UncertainLatency(), exceptionOut = Seq(illegalInstr) // TODO: need rewrite latency structure, not just this value, 622 ) 623 624 val csrCfg = FuConfig( 625 name = "csr", 626 fuGen = csrGen, 627 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 628 fuType = FuType.csr, 629 numIntSrc = 1, 630 numFpSrc = 0, 631 writeIntRf = true, 632 writeFpRf = false, 633 exceptionOut = Seq(illegalInstr, breakPoint, ecallU, ecallS, ecallM), 634 flushPipe = true 635 ) 636 637 val i2fCfg = FuConfig( 638 name = "i2f", 639 fuGen = i2fGen, 640 fuSel = i2fSel, 641 FuType.i2f, 642 numIntSrc = 1, 643 numFpSrc = 0, 644 writeIntRf = false, 645 writeFpRf = true, 646 writeFflags = true, 647 latency = CertainLatency(2), 648 fastUopOut = true, fastImplemented = true 649 ) 650 651 val divCfg = FuConfig( 652 name = "div", 653 fuGen = dividerGen, 654 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 655 FuType.div, 656 2, 657 0, 658 writeIntRf = true, 659 writeFpRf = false, 660 latency = UncertainLatency(), 661 fastUopOut = true, 662 fastImplemented = true 663 ) 664 665 val mulCfg = FuConfig( 666 name = "mul", 667 fuGen = multiplierGen, 668 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 669 FuType.mul, 670 2, 671 0, 672 writeIntRf = true, 673 writeFpRf = false, 674 latency = CertainLatency(2), 675 fastUopOut = true, 676 fastImplemented = true 677 ) 678 679 val bkuCfg = FuConfig( 680 name = "bku", 681 fuGen = bkuGen, 682 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 683 fuType = FuType.bku, 684 numIntSrc = 2, 685 numFpSrc = 0, 686 writeIntRf = true, 687 writeFpRf = false, 688 latency = CertainLatency(1), 689 fastUopOut = true, 690 fastImplemented = true 691 ) 692 693 val fmacCfg = FuConfig( 694 name = "fmac", 695 fuGen = fmacGen, 696 fuSel = _ => true.B, 697 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, writeFflags = true, 698 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 699 ) 700 701 val f2iCfg = FuConfig( 702 name = "f2i", 703 fuGen = f2iGen, 704 fuSel = f2iSel, 705 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, writeFflags = true, latency = CertainLatency(2), 706 fastUopOut = true, fastImplemented = true 707 ) 708 709 val f2fCfg = FuConfig( 710 name = "f2f", 711 fuGen = f2fGen, 712 fuSel = f2fSel, 713 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = CertainLatency(2), 714 fastUopOut = true, fastImplemented = true 715 ) 716 717 val fdivSqrtCfg = FuConfig( 718 name = "fdivSqrt", 719 fuGen = fdivSqrtGen, 720 fuSel = fdivSqrtSel, 721 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, writeFflags = true, latency = UncertainLatency(), 722 fastUopOut = true, fastImplemented = true, hasInputBuffer = true 723 ) 724 725 val lduCfg = FuConfig( 726 "ldu", 727 null, // DontCare 728 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 729 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, 730 latency = UncertainLatency(), 731 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault), 732 flushPipe = true, 733 replayInst = true, 734 hasLoadError = true 735 ) 736 737 val staCfg = FuConfig( 738 "sta", 739 null, 740 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 741 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, 742 latency = UncertainLatency(), 743 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault) 744 ) 745 746 val stdCfg = FuConfig( 747 "std", 748 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 749 writeIntRf = false, writeFpRf = false, latency = CertainLatency(1) 750 ) 751 752 val mouCfg = FuConfig( 753 "mou", 754 null, 755 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 756 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 757 latency = UncertainLatency(), exceptionOut = lduCfg.exceptionOut ++ staCfg.exceptionOut 758 ) 759 760 val mouDataCfg = FuConfig( 761 "mou", 762 mouDataGen, 763 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 764 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, 765 latency = UncertainLatency() 766 ) 767 768 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 769 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 770 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 771 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 772 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 773 val FmiscExeUnitCfg = ExuConfig( 774 "FmiscExeUnit", 775 "Fp", 776 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 777 Int.MaxValue, 1 778 ) 779 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 780 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 781 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 782} 783