1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import chisel3.internal.naming.chiselName 23import xiangshan._ 24import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 25import utils._ 26import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 27import freechips.rocketchip.tilelink._ 28 29/* ptw cache caches the page table of all the three layers 30 * ptw cache resp at next cycle 31 * the cache should not be blocked 32 * when miss queue if full, just block req outside 33 */ 34 35class PageCachePerPespBundle(implicit p: Parameters) extends PtwBundle { 36 val hit = Bool() 37 val pre = Bool() 38 val ppn = UInt(ppnLen.W) 39 val perm = new PtePermBundle() 40 val ecc = Bool() 41 val level = UInt(2.W) 42 val v = Bool() 43 44 def apply(hit: Bool, pre: Bool, ppn: UInt, perm: PtePermBundle = 0.U.asTypeOf(new PtePermBundle()), 45 ecc: Bool = false.B, level: UInt = 0.U, valid: Bool = true.B) { 46 this.hit := hit && !ecc 47 this.pre := pre 48 this.ppn := ppn 49 this.perm := perm 50 this.ecc := ecc && hit 51 this.level := level 52 this.v := valid 53 } 54} 55 56class PageCacheRespBundle(implicit p: Parameters) extends PtwBundle { 57 val l1 = new PageCachePerPespBundle 58 val l2 = new PageCachePerPespBundle 59 val l3 = new PageCachePerPespBundle 60 val sp = new PageCachePerPespBundle 61} 62 63class PtwCacheReq(implicit p: Parameters) extends PtwBundle { 64 val req_info = new L2TlbInnerBundle() 65 val isFirst = Bool() 66} 67 68class PtwCacheIO()(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwConst { 69 val req = Flipped(DecoupledIO(new PtwCacheReq())) 70 val resp = DecoupledIO(new Bundle { 71 val req_info = new L2TlbInnerBundle() 72 val isFirst = Bool() 73 val hit = Bool() 74 val prefetch = Bool() // is the entry fetched by prefetch 75 val toFsm = new Bundle { 76 val l1Hit = Bool() 77 val l2Hit = Bool() 78 val ppn = UInt(ppnLen.W) 79 } 80 val toTlb = new PtwEntry(tagLen = vpnLen, hasPerm = true, hasLevel = true) 81 }) 82 val refill = Flipped(ValidIO(new Bundle { 83 val ptes = UInt(blockBits.W) 84 val req_info = new L2TlbInnerBundle() 85 val level = UInt(log2Up(Level).W) 86 val addr_low = UInt((log2Up(l2tlbParams.blockBytes) - log2Up(XLEN/8)).W) 87 })) 88} 89 90@chiselName 91class PtwCache()(implicit p: Parameters) extends XSModule with HasPtwConst with HasPerfEvents { 92 val io = IO(new PtwCacheIO) 93 94 val ecc = Code.fromString(l2tlbParams.ecc) 95 val l2EntryType = new PTWEntriesWithEcc(ecc, num = PtwL2SectorSize, tagLen = PtwL2TagLen, level = 1, hasPerm = false) 96 val l3EntryType = new PTWEntriesWithEcc(ecc, num = PtwL3SectorSize, tagLen = PtwL3TagLen, level = 2, hasPerm = true) 97 98 // TODO: four caches make the codes dirty, think about how to deal with it 99 100 val sfence = io.sfence 101 val refill = io.refill.bits 102 val refill_prefetch = from_pre(io.refill.bits.req_info.source) 103 val flush = sfence.valid || io.csr.satp.changed 104 105 // when refill, refuce to accept new req 106 val rwHarzad = if (sramSinglePort) io.refill.valid else false.B 107 108 // handle hand signal and req_info 109 // TODO: replace with FlushableQueue 110 val stageReq = Wire(Decoupled(new PtwCacheReq())) // enq stage & read page cache valid 111 val stageDelay = Wire(Vec(2, Decoupled(new PtwCacheReq()))) // page cache resp 112 val stageCheck = Wire(Vec(2, Decoupled(new PtwCacheReq()))) // check hit & check ecc 113 val stageResp = Wire(Decoupled(new PtwCacheReq())) // deq stage 114 stageReq <> io.req 115 PipelineConnect(stageReq, stageDelay(0), stageDelay(1).ready, flush, rwHarzad) 116 InsideStageConnect(stageDelay(0), stageDelay(1)) 117 PipelineConnect(stageDelay(1), stageCheck(0), stageCheck(1).ready, flush) 118 InsideStageConnect(stageCheck(0), stageCheck(1)) 119 PipelineConnect(stageCheck(1), stageResp, io.resp.ready, flush) 120 stageResp.ready := !stageResp.valid || io.resp.ready 121 122 // l1: level 0 non-leaf pte 123 val l1 = Reg(Vec(l2tlbParams.l1Size, new PtwEntry(tagLen = PtwL1TagLen))) 124 val l1v = RegInit(0.U(l2tlbParams.l1Size.W)) 125 val l1g = Reg(UInt(l2tlbParams.l1Size.W)) 126 val l1asids = Reg(Vec(l2tlbParams.l1Size, UInt(AsidLength.W))) 127 128 // l2: level 1 non-leaf pte 129 val l2 = Module(new SRAMTemplate( 130 l2EntryType, 131 set = l2tlbParams.l2nSets, 132 way = l2tlbParams.l2nWays, 133 singlePort = sramSinglePort 134 )) 135 val l2v = RegInit(0.U((l2tlbParams.l2nSets * l2tlbParams.l2nWays).W)) 136 val l2g = Reg(UInt((l2tlbParams.l2nSets * l2tlbParams.l2nWays).W)) 137 val l2asids = Reg(Vec(l2tlbParams.l2nSets, Vec(l2tlbParams.l2nWays, UInt(AsidLength.W)))) 138 def getl2vSet(vpn: UInt) = { 139 require(log2Up(l2tlbParams.l2nWays) == log2Down(l2tlbParams.l2nWays)) 140 val set = genPtwL2SetIdx(vpn) 141 require(set.getWidth == log2Up(l2tlbParams.l2nSets)) 142 val l2vVec = l2v.asTypeOf(Vec(l2tlbParams.l2nSets, UInt(l2tlbParams.l2nWays.W))) 143 l2vVec(set) 144 } 145 def getl2asidSet(vpn: UInt) = { 146 require(log2Up(l2tlbParams.l2nWays) == log2Down(l2tlbParams.l2nWays)) 147 val set = genPtwL2SetIdx(vpn) 148 require(set.getWidth == log2Up(l2tlbParams.l2nSets)) 149 l2asids(set) 150 } 151 152 // l3: level 2 leaf pte of 4KB pages 153 val l3 = Module(new SRAMTemplate( 154 l3EntryType, 155 set = l2tlbParams.l3nSets, 156 way = l2tlbParams.l3nWays, 157 singlePort = sramSinglePort 158 )) 159 val l3v = RegInit(0.U((l2tlbParams.l3nSets * l2tlbParams.l3nWays).W)) 160 val l3g = Reg(UInt((l2tlbParams.l3nSets * l2tlbParams.l3nWays).W)) 161 val l3asids = Reg(Vec(l2tlbParams.l3nSets, Vec(l2tlbParams.l3nWays, UInt(AsidLength.W)))) 162 def getl3vSet(vpn: UInt) = { 163 require(log2Up(l2tlbParams.l3nWays) == log2Down(l2tlbParams.l3nWays)) 164 val set = genPtwL3SetIdx(vpn) 165 require(set.getWidth == log2Up(l2tlbParams.l3nSets)) 166 val l3vVec = l3v.asTypeOf(Vec(l2tlbParams.l3nSets, UInt(l2tlbParams.l3nWays.W))) 167 l3vVec(set) 168 } 169 def getl3asidSet(vpn: UInt) = { 170 require(log2Up(l2tlbParams.l3nWays) == log2Down(l2tlbParams.l3nWays)) 171 val set = genPtwL3SetIdx(vpn) 172 require(set.getWidth == log2Up(l2tlbParams.l3nSets)) 173 l3asids(set) 174 } 175 176 // sp: level 0/1 leaf pte of 1GB/2MB super pages 177 val sp = Reg(Vec(l2tlbParams.spSize, new PtwEntry(tagLen = SPTagLen, hasPerm = true, hasLevel = true))) 178 val spv = RegInit(0.U(l2tlbParams.spSize.W)) 179 val spg = Reg(UInt(l2tlbParams.spSize.W)) 180 val spasids = Reg(Vec(l2tlbParams.spSize, UInt(AsidLength.W))) 181 182 // Access Perf 183 val l1AccessPerf = Wire(Vec(l2tlbParams.l1Size, Bool())) 184 val l2AccessPerf = Wire(Vec(l2tlbParams.l2nWays, Bool())) 185 val l3AccessPerf = Wire(Vec(l2tlbParams.l3nWays, Bool())) 186 val spAccessPerf = Wire(Vec(l2tlbParams.spSize, Bool())) 187 l1AccessPerf.map(_ := false.B) 188 l2AccessPerf.map(_ := false.B) 189 l3AccessPerf.map(_ := false.B) 190 spAccessPerf.map(_ := false.B) 191 192 val stageDelay_valid_1cycle = OneCycleValid(stageReq.fire, flush) // catch ram data 193 val stageCheck_valid_1cycle = OneCycleValid(stageDelay(1).fire, flush) // replace & perf counter 194 val stageResp_valid_1cycle = OneCycleValid(stageCheck(1).fire, flush) // ecc flush 195 196 // l1 197 val ptwl1replace = ReplacementPolicy.fromString(l2tlbParams.l1Replacer, l2tlbParams.l1Size) 198 val (l1Hit, l1HitPPN, l1Pre) = { 199 val hitVecT = l1.zipWithIndex.map { case (e, i) => e.hit(stageReq.bits.req_info.vpn, io.csr.satp.asid) && l1v(i) } 200 val hitVec = hitVecT.map(RegEnable(_, stageReq.fire)) 201 val hitPPN = ParallelPriorityMux(hitVec zip l1.map(_.ppn)) 202 val hitPre = ParallelPriorityMux(hitVec zip l1.map(_.prefetch)) 203 val hit = ParallelOR(hitVec) 204 205 when (hit && stageDelay_valid_1cycle) { ptwl1replace.access(OHToUInt(hitVec)) } 206 207 l1AccessPerf.zip(hitVec).map{ case (l, h) => l := h && stageDelay_valid_1cycle} 208 for (i <- 0 until l2tlbParams.l1Size) { 209 XSDebug(stageReq.fire, p"[l1] l1(${i.U}) ${l1(i)} hit:${l1(i).hit(stageReq.bits.req_info.vpn, io.csr.satp.asid)}\n") 210 } 211 XSDebug(stageReq.fire, p"[l1] l1v:${Binary(l1v)} hitVecT:${Binary(VecInit(hitVecT).asUInt)}\n") 212 XSDebug(stageDelay(0).valid, p"[l1] l1Hit:${hit} l1HitPPN:0x${Hexadecimal(hitPPN)} hitVec:${VecInit(hitVec).asUInt}\n") 213 214 VecInit(hitVecT).suggestName(s"l1_hitVecT") 215 VecInit(hitVec).suggestName(s"l1_hitVec") 216 217 // synchronize with other entries with RegEnable 218 (RegEnable(hit, stageDelay(1).fire), 219 RegEnable(hitPPN, stageDelay(1).fire), 220 RegEnable(hitPre, stageDelay(1).fire)) 221 } 222 223 // l2 224 val ptwl2replace = ReplacementPolicy.fromString(l2tlbParams.l2Replacer,l2tlbParams.l2nWays,l2tlbParams.l2nSets) 225 val (l2Hit, l2HitPPN, l2Pre, l2eccError) = { 226 val ridx = genPtwL2SetIdx(stageReq.bits.req_info.vpn) 227 l2.io.r.req.valid := stageReq.fire 228 l2.io.r.req.bits.apply(setIdx = ridx) 229 230 // delay one cycle after sram read 231 val data_resp = DataHoldBypass(l2.io.r.resp.data, stageDelay_valid_1cycle) 232 233 // check hit and ecc 234 val check_vpn = stageCheck(0).bits.req_info.vpn 235 val ramDatas = RegEnable(data_resp, stageDelay(1).fire) 236 val vVec = getl2vSet(check_vpn).asBools 237 238 val hitVec = VecInit(ramDatas.zip(vVec).map { case (wayData, v) => 239 wayData.entries.hit(check_vpn, io.csr.satp.asid) && v }) 240 val hitWayEntry = ParallelPriorityMux(hitVec zip ramDatas) 241 val hitWayData = hitWayEntry.entries 242 val hit = ParallelOR(hitVec) 243 val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l2nWays).map(_.U)) 244 val eccError = hitWayEntry.decode() 245 246 ridx.suggestName(s"l2_ridx") 247 ramDatas.suggestName(s"l2_ramDatas") 248 hitVec.suggestName(s"l2_hitVec") 249 hitWayData.suggestName(s"l2_hitWayData") 250 hitWay.suggestName(s"l2_hitWay") 251 252 when (hit && stageCheck_valid_1cycle) { ptwl2replace.access(genPtwL2SetIdx(check_vpn), hitWay) } 253 254 l2AccessPerf.zip(hitVec).map{ case (l, h) => l := h && stageCheck_valid_1cycle } 255 XSDebug(stageDelay_valid_1cycle, p"[l2] ridx:0x${Hexadecimal(ridx)}\n") 256 for (i <- 0 until l2tlbParams.l2nWays) { 257 XSDebug(stageCheck_valid_1cycle, p"[l2] ramDatas(${i.U}) ${ramDatas(i)} l2v:${vVec(i)} hit:${hit}\n") 258 } 259 XSDebug(stageCheck_valid_1cycle, p"[l2] l2Hit:${hit} l2HitPPN:0x${Hexadecimal(hitWayData.ppns(genPtwL2SectorIdx(check_vpn)))} hitVec:${Binary(hitVec.asUInt)} hitWay:${hitWay} vidx:${vVec}\n") 260 261 (hit, hitWayData.ppns(genPtwL2SectorIdx(check_vpn)), hitWayData.prefetch, eccError) 262 } 263 264 // l3 265 val ptwl3replace = ReplacementPolicy.fromString(l2tlbParams.l3Replacer,l2tlbParams.l3nWays,l2tlbParams.l3nSets) 266 val (l3Hit, l3HitData, l3Pre, l3eccError) = { 267 val ridx = genPtwL3SetIdx(stageReq.bits.req_info.vpn) 268 l3.io.r.req.valid := stageReq.fire 269 l3.io.r.req.bits.apply(setIdx = ridx) 270 271 // delay one cycle after sram read 272 val data_resp = DataHoldBypass(l3.io.r.resp.data, stageDelay_valid_1cycle) 273 274 // check hit and ecc 275 val check_vpn = stageCheck(0).bits.req_info.vpn 276 val ramDatas = RegEnable(data_resp, stageDelay(1).fire) 277 val vVec = getl3vSet(check_vpn).asBools 278 279 val hitVec = VecInit(ramDatas.zip(vVec).map{ case (wayData, v) => 280 wayData.entries.hit(check_vpn, io.csr.satp.asid) && v }) 281 val hitWayEntry = ParallelPriorityMux(hitVec zip ramDatas) 282 val hitWayData = hitWayEntry.entries 283 val hitWayEcc = hitWayEntry.ecc 284 val hit = ParallelOR(hitVec) 285 val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l3nWays).map(_.U)) 286 val eccError = hitWayEntry.decode() 287 288 when (hit && stageCheck_valid_1cycle) { ptwl3replace.access(genPtwL3SetIdx(check_vpn), hitWay) } 289 290 l3AccessPerf.zip(hitVec).map{ case (l, h) => l := h && stageCheck_valid_1cycle } 291 XSDebug(stageReq.fire, p"[l3] ridx:0x${Hexadecimal(ridx)}\n") 292 for (i <- 0 until l2tlbParams.l3nWays) { 293 XSDebug(stageCheck_valid_1cycle, p"[l3] ramDatas(${i.U}) ${ramDatas(i)} l3v:${vVec(i)} hit:${hitVec(i)}\n") 294 } 295 XSDebug(stageCheck_valid_1cycle, p"[l3] l3Hit:${hit} l3HitData:${hitWayData} hitVec:${Binary(hitVec.asUInt)} hitWay:${hitWay} v:${vVec}\n") 296 297 ridx.suggestName(s"l3_ridx") 298 ramDatas.suggestName(s"l3_ramDatas") 299 hitVec.suggestName(s"l3_hitVec") 300 hitWay.suggestName(s"l3_hitWay") 301 302 (hit, hitWayData, hitWayData.prefetch, eccError) 303 } 304 val l3HitPPN = l3HitData.ppns(genPtwL3SectorIdx(stageCheck(0).bits.req_info.vpn)) 305 val l3HitPerm = l3HitData.perms.getOrElse(0.U.asTypeOf(Vec(PtwL3SectorSize, new PtePermBundle)))(genPtwL3SectorIdx(stageCheck(0).bits.req_info.vpn)) 306 307 // super page 308 val spreplace = ReplacementPolicy.fromString(l2tlbParams.spReplacer, l2tlbParams.spSize) 309 val (spHit, spHitData, spPre, spValid) = { 310 val hitVecT = sp.zipWithIndex.map { case (e, i) => e.hit(stageReq.bits.req_info.vpn, io.csr.satp.asid) && spv(i) } 311 val hitVec = hitVecT.map(RegEnable(_, stageReq.fire)) 312 val hitData = ParallelPriorityMux(hitVec zip sp) 313 val hit = ParallelOR(hitVec) 314 315 when (hit && stageDelay_valid_1cycle) { spreplace.access(OHToUInt(hitVec)) } 316 317 spAccessPerf.zip(hitVec).map{ case (s, h) => s := h && stageDelay_valid_1cycle } 318 for (i <- 0 until l2tlbParams.spSize) { 319 XSDebug(stageReq.fire, p"[sp] sp(${i.U}) ${sp(i)} hit:${sp(i).hit(stageReq.bits.req_info.vpn, io.csr.satp.asid)} spv:${spv(i)}\n") 320 } 321 XSDebug(stageDelay_valid_1cycle, p"[sp] spHit:${hit} spHitData:${hitData} hitVec:${Binary(VecInit(hitVec).asUInt)}\n") 322 323 VecInit(hitVecT).suggestName(s"sp_hitVecT") 324 VecInit(hitVec).suggestName(s"sp_hitVec") 325 326 (RegEnable(hit, stageDelay(1).fire), 327 RegEnable(hitData, stageDelay(1).fire), 328 RegEnable(hitData.prefetch, stageDelay(1).fire), 329 RegEnable(hitData.v, stageDelay(1).fire())) 330 } 331 val spHitPerm = spHitData.perm.getOrElse(0.U.asTypeOf(new PtePermBundle)) 332 val spHitLevel = spHitData.level.getOrElse(0.U) 333 334 val check_res = Wire(new PageCacheRespBundle) 335 check_res.l1.apply(l1Hit, l1Pre, l1HitPPN) 336 check_res.l2.apply(l2Hit, l2Pre, l2HitPPN, ecc = l2eccError) 337 check_res.l3.apply(l3Hit, l3Pre, l3HitPPN, l3HitPerm, l3eccError) 338 check_res.sp.apply(spHit, spPre, spHitData.ppn, spHitPerm, false.B, spHitLevel, spValid) 339 340 // stage3, add stage 3 for ecc check... 341 val resp_res = Reg(new PageCacheRespBundle) 342 when (stageCheck(1).fire) { resp_res := check_res } 343 344 io.resp.bits.req_info := stageResp.bits.req_info 345 io.resp.bits.isFirst := stageResp.bits.isFirst 346 io.resp.bits.hit := resp_res.l3.hit || resp_res.sp.hit 347 io.resp.bits.prefetch := resp_res.l3.pre && resp_res.l3.hit || resp_res.sp.pre && resp_res.sp.hit 348 io.resp.bits.toFsm.l1Hit := resp_res.l1.hit 349 io.resp.bits.toFsm.l2Hit := resp_res.l2.hit 350 io.resp.bits.toFsm.ppn := Mux(resp_res.l2.hit, resp_res.l2.ppn, resp_res.l1.ppn) 351 io.resp.bits.toTlb.tag := stageResp.bits.req_info.vpn 352 io.resp.bits.toTlb.asid := io.csr.satp.asid // DontCare 353 io.resp.bits.toTlb.ppn := Mux(resp_res.l3.hit, resp_res.l3.ppn, resp_res.sp.ppn) 354 io.resp.bits.toTlb.perm.map(_ := Mux(resp_res.l3.hit, resp_res.l3.perm, resp_res.sp.perm)) 355 io.resp.bits.toTlb.level.map(_ := Mux(resp_res.l3.hit, 2.U, resp_res.sp.level)) 356 io.resp.bits.toTlb.prefetch := from_pre(stageResp.bits.req_info.source) 357 io.resp.bits.toTlb.v := Mux(resp_res.sp.hit, resp_res.sp.v, resp_res.l3.v) 358 io.resp.valid := stageResp.valid 359 XSError(stageResp.valid && resp_res.l3.hit && resp_res.sp.hit, "normal page and super page both hit") 360 361 // refill Perf 362 val l1RefillPerf = Wire(Vec(l2tlbParams.l1Size, Bool())) 363 val l2RefillPerf = Wire(Vec(l2tlbParams.l2nWays, Bool())) 364 val l3RefillPerf = Wire(Vec(l2tlbParams.l3nWays, Bool())) 365 val spRefillPerf = Wire(Vec(l2tlbParams.spSize, Bool())) 366 l1RefillPerf.map(_ := false.B) 367 l2RefillPerf.map(_ := false.B) 368 l3RefillPerf.map(_ := false.B) 369 spRefillPerf.map(_ := false.B) 370 371 // refill 372 l2.io.w.req <> DontCare 373 l3.io.w.req <> DontCare 374 l2.io.w.req.valid := false.B 375 l3.io.w.req.valid := false.B 376 377 def get_part(data: UInt, index: UInt): UInt = { 378 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 379 inner_data(index) 380 } 381 382 val memRdata = refill.ptes 383 val memSelData = get_part(memRdata, refill.addr_low) 384 val memPtes = (0 until (l2tlbParams.blockBytes/(XLEN/8))).map(i => memRdata((i+1)*XLEN-1, i*XLEN).asTypeOf(new PteBundle)) 385 val memPte = memSelData.asTypeOf(new PteBundle) 386 387 memPte.suggestName("memPte") 388 389 // TODO: handle sfenceLatch outsize 390 when (io.refill.valid && !memPte.isPf(refill.level) && !flush ) { 391 when (refill.level === 0.U && !memPte.isLeaf()) { 392 // val refillIdx = LFSR64()(log2Up(l2tlbParams.l1Size)-1,0) // TODO: may be LRU 393 val refillIdx = replaceWrapper(l1v, ptwl1replace.way) 394 refillIdx.suggestName(s"PtwL1RefillIdx") 395 val rfOH = UIntToOH(refillIdx) 396 l1(refillIdx).refill( 397 refill.req_info.vpn, 398 io.csr.satp.asid, 399 memSelData, 400 0.U, 401 refill_prefetch 402 ) 403 ptwl1replace.access(refillIdx) 404 l1v := l1v | rfOH 405 l1g := (l1g & ~rfOH) | Mux(memPte.perm.g, rfOH, 0.U) 406 407 for (i <- 0 until l2tlbParams.l1Size) { 408 l1RefillPerf(i) := i.U === refillIdx 409 } 410 411 XSDebug(p"[l1 refill] refillIdx:${refillIdx} refillEntry:${l1(refillIdx).genPtwEntry(refill.req_info.vpn, io.csr.satp.asid, memSelData, 0.U, prefetch = refill_prefetch)}\n") 412 XSDebug(p"[l1 refill] l1v:${Binary(l1v)}->${Binary(l1v | rfOH)} l1g:${Binary(l1g)}->${Binary((l1g & ~rfOH) | Mux(memPte.perm.g, rfOH, 0.U))}\n") 413 414 refillIdx.suggestName(s"l1_refillIdx") 415 rfOH.suggestName(s"l1_rfOH") 416 } 417 418 when (refill.level === 1.U && !memPte.isLeaf()) { 419 val refillIdx = genPtwL2SetIdx(refill.req_info.vpn) 420 val victimWay = replaceWrapper(getl2vSet(refill.req_info.vpn), ptwl2replace.way(refillIdx)) 421 val victimWayOH = UIntToOH(victimWay) 422 val rfvOH = UIntToOH(Cat(refillIdx, victimWay)) 423 val wdata = Wire(l2EntryType) 424 wdata.gen( 425 vpn = refill.req_info.vpn, 426 asid = io.csr.satp.asid, 427 data = memRdata, 428 levelUInt = 1.U, 429 refill_prefetch 430 ) 431 l2.io.w.apply( 432 valid = true.B, 433 setIdx = refillIdx, 434 data = wdata, 435 waymask = victimWayOH 436 ) 437 ptwl2replace.access(refillIdx, victimWay) 438 l2v := l2v | rfvOH 439 l2g := l2g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U) 440 441 for (i <- 0 until l2tlbParams.l2nWays) { 442 l2RefillPerf(i) := i.U === victimWay 443 } 444 445 XSDebug(p"[l2 refill] refillIdx:0x${Hexadecimal(refillIdx)} victimWay:${victimWay} victimWayOH:${Binary(victimWayOH)} rfvOH(in UInt):${Cat(refillIdx, victimWay)}\n") 446 XSDebug(p"[l2 refill] refilldata:0x${wdata}\n") 447 XSDebug(p"[l2 refill] l2v:${Binary(l2v)} -> ${Binary(l2v | rfvOH)}\n") 448 XSDebug(p"[l2 refill] l2g:${Binary(l2g)} -> ${Binary(l2g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U))}\n") 449 450 refillIdx.suggestName(s"l2_refillIdx") 451 victimWay.suggestName(s"l2_victimWay") 452 victimWayOH.suggestName(s"l2_victimWayOH") 453 rfvOH.suggestName(s"l2_rfvOH") 454 } 455 456 when (refill.level === 2.U && memPte.isLeaf()) { 457 val refillIdx = genPtwL3SetIdx(refill.req_info.vpn) 458 val victimWay = replaceWrapper(getl3vSet(refill.req_info.vpn), ptwl3replace.way(refillIdx)) 459 val victimWayOH = UIntToOH(victimWay) 460 val rfvOH = UIntToOH(Cat(refillIdx, victimWay)) 461 val wdata = Wire(l3EntryType) 462 wdata.gen( 463 vpn = refill.req_info.vpn, 464 asid = io.csr.satp.asid, 465 data = memRdata, 466 levelUInt = 2.U, 467 refill_prefetch 468 ) 469 l3.io.w.apply( 470 valid = true.B, 471 setIdx = refillIdx, 472 data = wdata, 473 waymask = victimWayOH 474 ) 475 ptwl3replace.access(refillIdx, victimWay) 476 l3v := l3v | rfvOH 477 l3g := l3g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U) 478 479 for (i <- 0 until l2tlbParams.l3nWays) { 480 l3RefillPerf(i) := i.U === victimWay 481 } 482 483 XSDebug(p"[l3 refill] refillIdx:0x${Hexadecimal(refillIdx)} victimWay:${victimWay} victimWayOH:${Binary(victimWayOH)} rfvOH(in UInt):${Cat(refillIdx, victimWay)}\n") 484 XSDebug(p"[l3 refill] refilldata:0x${wdata}\n") 485 XSDebug(p"[l3 refill] l3v:${Binary(l3v)} -> ${Binary(l3v | rfvOH)}\n") 486 XSDebug(p"[l3 refill] l3g:${Binary(l3g)} -> ${Binary(l3g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U))}\n") 487 488 refillIdx.suggestName(s"l3_refillIdx") 489 victimWay.suggestName(s"l3_victimWay") 490 victimWayOH.suggestName(s"l3_victimWayOH") 491 rfvOH.suggestName(s"l3_rfvOH") 492 } 493 } 494 495 // misc entries: super & invalid 496 when (io.refill.valid && !flush && (refill.level === 0.U || refill.level === 1.U) && (memPte.isLeaf() || memPte.isPf(refill.level))) { 497 val refillIdx = spreplace.way// LFSR64()(log2Up(l2tlbParams.spSize)-1,0) // TODO: may be LRU 498 val rfOH = UIntToOH(refillIdx) 499 sp(refillIdx).refill( 500 refill.req_info.vpn, 501 io.csr.satp.asid, 502 memSelData, 503 refill.level, 504 refill_prefetch, 505 !memPte.isPf(refill.level), 506 ) 507 spreplace.access(refillIdx) 508 spv := spv | rfOH 509 spg := spg & ~rfOH | Mux(memPte.perm.g, rfOH, 0.U) 510 511 for (i <- 0 until l2tlbParams.spSize) { 512 spRefillPerf(i) := i.U === refillIdx 513 } 514 515 XSDebug(p"[sp refill] refillIdx:${refillIdx} refillEntry:${sp(refillIdx).genPtwEntry(refill.req_info.vpn, io.csr.satp.asid, memSelData, refill.level, refill_prefetch)}\n") 516 XSDebug(p"[sp refill] spv:${Binary(spv)}->${Binary(spv | rfOH)} spg:${Binary(spg)}->${Binary(spg & ~rfOH | Mux(memPte.perm.g, rfOH, 0.U))}\n") 517 518 refillIdx.suggestName(s"sp_refillIdx") 519 rfOH.suggestName(s"sp_rfOH") 520 } 521 522 val l2eccFlush = resp_res.l2.ecc && stageResp_valid_1cycle // RegNext(l2eccError, init = false.B) 523 val l3eccFlush = resp_res.l3.ecc && stageResp_valid_1cycle // RegNext(l3eccError, init = false.B) 524 val eccVpn = stageResp.bits.req_info.vpn 525 526 XSError(l2eccFlush, "l2tlb.cache.l2 ecc error. Should not happen at sim stage") 527 XSError(l3eccFlush, "l2tlb.cache.l3 ecc error. Should not happen at sim stage") 528 when (l2eccFlush) { 529 val flushSetIdxOH = UIntToOH(genPtwL2SetIdx(eccVpn)) 530 val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l2nWays, a.asUInt) }).asUInt 531 l2v := l2v & ~flushMask 532 l2g := l2g & ~flushMask 533 } 534 535 when (l3eccFlush) { 536 val flushSetIdxOH = UIntToOH(genPtwL3SetIdx(eccVpn)) 537 val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l3nWays, a.asUInt) }).asUInt 538 l3v := l3v & ~flushMask 539 l3g := l3g & ~flushMask 540 } 541 542 // sfence 543 when (sfence.valid) { 544 val l1asidhit = VecInit(l1asids.map(_ === sfence.bits.asid)).asUInt 545 val spasidhit = VecInit(spasids.map(_ === sfence.bits.asid)).asUInt 546 val sfence_vpn = sfence.bits.addr(sfence.bits.addr.getWidth-1, offLen) 547 548 when (sfence.bits.rs1/*va*/) { 549 when (sfence.bits.rs2) { 550 // all va && all asid 551 l1v := 0.U 552 l2v := 0.U 553 l3v := 0.U 554 spv := 0.U 555 } .otherwise { 556 // all va && specific asid except global 557 558 l1v := l1v & (~l1asidhit | l1g) 559 l2v := l2v & l2g 560 l3v := l3v & l3g 561 spv := spv & (~spasidhit | spg) 562 } 563 } .otherwise { 564 // val flushMask = UIntToOH(genTlbL2Idx(sfence.bits.addr(sfence.bits.addr.getWidth-1, offLen))) 565 val flushSetIdxOH = UIntToOH(genPtwL3SetIdx(sfence_vpn)) 566 // val flushMask = VecInit(flushSetIdxOH.asBools.map(Fill(l2tlbParams.l3nWays, _.asUInt))).asUInt 567 val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l3nWays, a.asUInt) }).asUInt 568 flushSetIdxOH.suggestName(s"sfence_nrs1_flushSetIdxOH") 569 flushMask.suggestName(s"sfence_nrs1_flushMask") 570 571 when (sfence.bits.rs2) { 572 // specific leaf of addr && all asid 573 l3v := l3v & ~flushMask 574 spv := spv & (~VecInit(sp.map(_.hit(sfence_vpn, sfence.bits.asid, ignoreAsid = true))).asUInt | spg) 575 } .otherwise { 576 // specific leaf of addr && specific asid 577 l3v := l3v & (~flushMask | l3g) 578 spv := spv & (~VecInit(sp.map(_.hit(sfence_vpn, sfence.bits.asid))).asUInt | spg) 579 } 580 } 581 } 582 583 def InsideStageConnect[T <:Data](in: DecoupledIO[T], out: DecoupledIO[T], block: Bool = false.B): Unit = { 584 in.ready := !in.valid || out.ready 585 out.valid := in.valid 586 out.bits := in.bits 587 } 588 589 // Perf Count 590 val resp_l3 = resp_res.l3.hit 591 val resp_sp = resp_res.sp.hit 592 val resp_l1_pre = resp_res.l1.pre 593 val resp_l2_pre = resp_res.l2.pre 594 val resp_l3_pre = resp_res.l3.pre 595 val resp_sp_pre = resp_res.sp.pre 596 val base_valid_access_0 = !from_pre(io.resp.bits.req_info.source) && io.resp.fire() 597 XSPerfAccumulate("access", base_valid_access_0) 598 XSPerfAccumulate("l1_hit", base_valid_access_0 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 599 XSPerfAccumulate("l2_hit", base_valid_access_0 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 600 XSPerfAccumulate("l3_hit", base_valid_access_0 && resp_l3) 601 XSPerfAccumulate("sp_hit", base_valid_access_0 && resp_sp) 602 XSPerfAccumulate("pte_hit",base_valid_access_0 && io.resp.bits.hit) 603 604 XSPerfAccumulate("l1_hit_pre", base_valid_access_0 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 605 XSPerfAccumulate("l2_hit_pre", base_valid_access_0 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 606 XSPerfAccumulate("l3_hit_pre", base_valid_access_0 && resp_l3_pre && resp_l3) 607 XSPerfAccumulate("sp_hit_pre", base_valid_access_0 && resp_sp_pre && resp_sp) 608 XSPerfAccumulate("pte_hit_pre",base_valid_access_0 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 609 610 val base_valid_access_1 = from_pre(io.resp.bits.req_info.source) && io.resp.fire() 611 XSPerfAccumulate("pre_access", base_valid_access_1) 612 XSPerfAccumulate("pre_l1_hit", base_valid_access_1 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 613 XSPerfAccumulate("pre_l2_hit", base_valid_access_1 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 614 XSPerfAccumulate("pre_l3_hit", base_valid_access_1 && resp_l3) 615 XSPerfAccumulate("pre_sp_hit", base_valid_access_1 && resp_sp) 616 XSPerfAccumulate("pre_pte_hit",base_valid_access_1 && io.resp.bits.hit) 617 618 XSPerfAccumulate("pre_l1_hit_pre", base_valid_access_1 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 619 XSPerfAccumulate("pre_l2_hit_pre", base_valid_access_1 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 620 XSPerfAccumulate("pre_l3_hit_pre", base_valid_access_1 && resp_l3_pre && resp_l3) 621 XSPerfAccumulate("pre_sp_hit_pre", base_valid_access_1 && resp_sp_pre && resp_sp) 622 XSPerfAccumulate("pre_pte_hit_pre",base_valid_access_1 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 623 624 val base_valid_access_2 = stageResp.bits.isFirst && !from_pre(io.resp.bits.req_info.source) && io.resp.fire() 625 XSPerfAccumulate("access_first", base_valid_access_2) 626 XSPerfAccumulate("l1_hit_first", base_valid_access_2 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 627 XSPerfAccumulate("l2_hit_first", base_valid_access_2 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 628 XSPerfAccumulate("l3_hit_first", base_valid_access_2 && resp_l3) 629 XSPerfAccumulate("sp_hit_first", base_valid_access_2 && resp_sp) 630 XSPerfAccumulate("pte_hit_first",base_valid_access_2 && io.resp.bits.hit) 631 632 XSPerfAccumulate("l1_hit_pre_first", base_valid_access_2 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 633 XSPerfAccumulate("l2_hit_pre_first", base_valid_access_2 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 634 XSPerfAccumulate("l3_hit_pre_first", base_valid_access_2 && resp_l3_pre && resp_l3) 635 XSPerfAccumulate("sp_hit_pre_first", base_valid_access_2 && resp_sp_pre && resp_sp) 636 XSPerfAccumulate("pte_hit_pre_first",base_valid_access_2 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 637 638 val base_valid_access_3 = stageResp.bits.isFirst && from_pre(io.resp.bits.req_info.source) && io.resp.fire() 639 XSPerfAccumulate("pre_access_first", base_valid_access_3) 640 XSPerfAccumulate("pre_l1_hit_first", base_valid_access_3 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 641 XSPerfAccumulate("pre_l2_hit_first", base_valid_access_3 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 642 XSPerfAccumulate("pre_l3_hit_first", base_valid_access_3 && resp_l3) 643 XSPerfAccumulate("pre_sp_hit_first", base_valid_access_3 && resp_sp) 644 XSPerfAccumulate("pre_pte_hit_first", base_valid_access_3 && io.resp.bits.hit) 645 646 XSPerfAccumulate("pre_l1_hit_pre_first", base_valid_access_3 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 647 XSPerfAccumulate("pre_l2_hit_pre_first", base_valid_access_3 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 648 XSPerfAccumulate("pre_l3_hit_pre_first", base_valid_access_3 && resp_l3_pre && resp_l3) 649 XSPerfAccumulate("pre_sp_hit_pre_first", base_valid_access_3 && resp_sp_pre && resp_sp) 650 XSPerfAccumulate("pre_pte_hit_pre_first",base_valid_access_3 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 651 652 XSPerfAccumulate("rwHarzad", io.req.valid && !io.req.ready) 653 XSPerfAccumulate("out_blocked", io.resp.valid && !io.resp.ready) 654 l1AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L1AccessIndex${i}", l) } 655 l2AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L2AccessIndex${i}", l) } 656 l3AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L3AccessIndex${i}", l) } 657 spAccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"SPAccessIndex${i}", l) } 658 l1RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L1RefillIndex${i}", l) } 659 l2RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L2RefillIndex${i}", l) } 660 l3RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L3RefillIndex${i}", l) } 661 spRefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"SPRefillIndex${i}", l) } 662 663 XSPerfAccumulate("l1Refill", Cat(l1RefillPerf).orR) 664 XSPerfAccumulate("l2Refill", Cat(l2RefillPerf).orR) 665 XSPerfAccumulate("l3Refill", Cat(l3RefillPerf).orR) 666 XSPerfAccumulate("spRefill", Cat(spRefillPerf).orR) 667 XSPerfAccumulate("l1Refill_pre", Cat(l1RefillPerf).orR && refill_prefetch) 668 XSPerfAccumulate("l2Refill_pre", Cat(l2RefillPerf).orR && refill_prefetch) 669 XSPerfAccumulate("l3Refill_pre", Cat(l3RefillPerf).orR && refill_prefetch) 670 XSPerfAccumulate("spRefill_pre", Cat(spRefillPerf).orR && refill_prefetch) 671 672 // debug 673 XSDebug(sfence.valid, p"[sfence] original v and g vector:\n") 674 XSDebug(sfence.valid, p"[sfence] l1v:${Binary(l1v)}\n") 675 XSDebug(sfence.valid, p"[sfence] l2v:${Binary(l2v)}\n") 676 XSDebug(sfence.valid, p"[sfence] l3v:${Binary(l3v)}\n") 677 XSDebug(sfence.valid, p"[sfence] l3g:${Binary(l3g)}\n") 678 XSDebug(sfence.valid, p"[sfence] spv:${Binary(spv)}\n") 679 XSDebug(RegNext(sfence.valid), p"[sfence] new v and g vector:\n") 680 XSDebug(RegNext(sfence.valid), p"[sfence] l1v:${Binary(l1v)}\n") 681 XSDebug(RegNext(sfence.valid), p"[sfence] l2v:${Binary(l2v)}\n") 682 XSDebug(RegNext(sfence.valid), p"[sfence] l3v:${Binary(l3v)}\n") 683 XSDebug(RegNext(sfence.valid), p"[sfence] l3g:${Binary(l3g)}\n") 684 XSDebug(RegNext(sfence.valid), p"[sfence] spv:${Binary(spv)}\n") 685 686 val perfEvents = Seq( 687 ("access ", base_valid_access_0 ), 688 ("l1_hit ", l1Hit ), 689 ("l2_hit ", l2Hit ), 690 ("l3_hit ", l3Hit ), 691 ("sp_hit ", spHit ), 692 ("pte_hit ", l3Hit || spHit ), 693 ("rwHarzad ", io.req.valid && !io.req.ready ), 694 ("out_blocked ", io.resp.valid && !io.resp.ready), 695 ) 696 generatePerfEvent() 697} 698