xref: /XiangShan/src/main/scala/xiangshan/backend/issue/BypassNetwork.scala (revision 9658ce50e75af9566868a3e788b4888e8be1859f) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.backend.issue
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import xiangshan._
23import utils._
24
25
26class BypassInfo(numWays: Int, dataBits: Int) extends Bundle {
27  val valid = Vec(numWays, Bool())
28  val data = UInt(dataBits.W)
29
30}
31
32class BypassNetworkIO(numWays: Int, numBypass: Int, dataBits: Int) extends Bundle {
33  val hold = Input(Bool())
34  val source = Vec(numWays, Input(UInt(dataBits.W)))
35  val target = Vec(numWays, Output(UInt(dataBits.W)))
36  val bypass = Vec(numBypass, Input(new BypassInfo(numWays, dataBits)))
37
38}
39
40class BypassNetwork(numWays: Int, numBypass: Int, dataBits: Int)(implicit p: Parameters)
41  extends XSModule {
42
43  val io = IO(new BypassNetworkIO(numWays, numBypass, dataBits))
44
45  def doBypass(bypassValid: Seq[Bool], bypassData: Seq[UInt], baseData: UInt, debugIndex: Int = 0): UInt = {
46    val bypassVec = VecInit(bypassValid)
47    val target = Mux(bypassVec.asUInt.orR, Mux1H(bypassValid, bypassData), baseData)
48
49    XSError(PopCount(bypassVec) > 1.U, p"bypass mask ${Binary(bypassVec.asUInt)} is not one-hot\n")
50    bypassVec.zipWithIndex.map { case (m, i) =>
51      XSDebug(bypassVec(i), p"target($debugIndex) bypassed from $i:0x${Hexadecimal(bypassData(i))}\n")
52    }
53
54    target
55  }
56
57}
58
59// Bypass at the right: RegNext(data) and compute the bypassed data at the next clock cycle
60class BypassNetworkRight(numWays: Int, numBypass: Int, dataBits: Int)(implicit p: Parameters)
61  extends BypassNetwork(numWays, numBypass, dataBits) {
62
63  val target_reg = Reg(Vec(numWays, UInt(dataBits.W)))
64  val bypass_reg = Reg(Vec(numBypass, new BypassInfo(numWays, dataBits)))
65
66  when (io.hold) {
67    target_reg := io.target
68    bypass_reg.map(_.valid.map(_ := false.B))
69  }.otherwise {
70    target_reg := io.source
71    for ((by_reg, by_io) <- bypass_reg.zip(io.bypass)) {
72      by_reg.data := by_io.data
73      by_reg.valid := by_io.valid
74    }
75  }
76
77  // bypass data to target
78  for (i <- 0 until numWays) {
79    io.target(i) := doBypass(bypass_reg.map(_.valid(i)), bypass_reg.map(_.data), target_reg(i))
80  }
81
82}
83
84// Bypass at the left: compute the bypassed data and RegNext(bypassed_data)
85class BypassNetworkLeft(numWays: Int, numBypass: Int, dataBits: Int)(implicit p: Parameters)
86  extends BypassNetwork(numWays, numBypass, dataBits) {
87
88  val bypassedData = Reg(io.target.cloneType)
89
90  when (!io.hold) {
91    for ((by, i) <- bypassedData.zipWithIndex) {
92      by := doBypass(io.bypass.map(_.valid(i)), io.bypass.map(_.data), io.source(i))
93    }
94  }
95
96  io.target := bypassedData
97
98}
99
100object BypassNetwork {
101  def apply(numWays: Int, numBypass: Int, dataBits: Int, optFirstStage: Boolean)(implicit p: Parameters) = {
102    Module(new BypassNetworkLeft(numWays, numBypass, dataBits))
103  }
104}
105