| #
303b861d |
| 07-Nov-2019 |
Zihao Yu <[email protected]> |
system,SoC: add instruction trace signals for ILA
|
| #
eb8bdfa7 |
| 06-Nov-2019 |
Zihao Yu <[email protected]> |
Merge branch 'master' into l2cache
|
| #
635253aa |
| 31-Oct-2019 |
Zihao Yu <[email protected]> |
system,CoherenceInterconnect: break deadlock by splitting the probe state machine from xbar
|
| #
096ea47e |
| 29-Oct-2019 |
zhanglinjuan <[email protected]> |
fix l2 cache bug
|
| #
5704b623 |
| 22-Oct-2019 |
zhanglinjuan <[email protected]> |
add l2 cache. TODO: handle readBurst req
|
| #
466eb0a8 |
| 07-Oct-2019 |
Zihao Yu <[email protected]> |
system,SoC: add meip
|
| #
5d41d760 |
| 05-Oct-2019 |
Zihao Yu <[email protected]> |
system,SoC: synchronize mtip
|
| #
fe820c3d |
| 01-Oct-2019 |
Zihao Yu <[email protected]> |
noop,fu,CSR: add mie and mip for machine timer interrupt
TODO:
* Injecting interrupts in decode stage with NOP.
* Save mstatus.mie to mstatus.mpie
|
| #
ad255e6c |
| 07-Sep-2019 |
Zihao Yu <[email protected]> |
bus,SimpleBus: unify SimpleBusUL and SimpleBusUH
|
| #
cdd59e9f |
| 03-Sep-2019 |
Zihao Yu <[email protected]> |
system: add coherence manager framework
|
| #
8f36f779 |
| 01-Sep-2019 |
Zihao Yu <[email protected]> |
bus,simplebus: divide into SimpleBusUL and SimpleBusUH
* SimpleBusUL is used for MMIO and SimpleBusUH is used for memory
* should refactor SimpleBus2AXI4Converter to support SimpleBusUL and
Simple
bus,simplebus: divide into SimpleBusUL and SimpleBusUH
* SimpleBusUL is used for MMIO and SimpleBusUH is used for memory
* should refactor SimpleBus2AXI4Converter to support SimpleBusUL and
SimpleBusUH
show more ...
|
| #
006e1884 |
| 01-Sep-2019 |
Zihao Yu <[email protected]> |
system: add SoC level
|