xref: /XiangShan/src/main/scala/system/SoC.scala (revision ad255e6ca3b25c1827d4033032c047e82e44b7b8) 
1package system
2
3import noop.{NOOP, NOOPConfig}
4import bus.axi4.{AXI4, AXI4Lite}
5import bus.simplebus._
6
7import chisel3._
8
9class NOOPSoC(implicit val p: NOOPConfig) extends Module {
10  val io = IO(new Bundle{
11    val mem = new AXI4
12    val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
13  })
14
15  val noop = Module(new NOOP)
16  val cohMg = Module(new CoherenceInterconnect)
17  cohMg.io.in(0) <> noop.io.imem
18  cohMg.io.in(1) <> noop.io.dmem
19  io.mem <> cohMg.io.out.toAXI4()
20
21  if (p.FPGAPlatform) io.mmio <> noop.io.mmio.toAXI4Lite()
22  else io.mmio <> noop.io.mmio
23}
24