xref: /XiangShan/src/main/scala/system/SoC.scala (revision eb8bdfa799772363d7ec3353db0f1f5a2730aa8f) 
1package system
2
3import noop._
4import bus.axi4.{AXI4, AXI4Lite}
5import bus.simplebus._
6
7import chisel3._
8import chisel3.util._
9import chisel3.util.experimental.BoringUtils
10
11class NOOPSoC(implicit val p: NOOPConfig) extends NOOPModule {
12  val io = IO(new Bundle{
13    val mem = new AXI4
14    val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
15    val mtip = Input(Bool())
16    val meip = Input(Bool())
17  })
18
19  val noop = Module(new NOOP)
20
21  val cohMg = Module(new CoherenceManager)
22  val xbar = Module(new SimpleBusCrossbarNto1(2))
23  cohMg.io.in <> noop.io.imem.mem
24  noop.io.dmem.coh <> cohMg.io.out.coh
25  xbar.io.in(0) <> cohMg.io.out.mem
26  xbar.io.in(1) <> noop.io.dmem.mem
27
28  if (HasL2cache) {
29    val l2cacheOut = Wire(new SimpleBusUC)
30    l2cacheOut <> Cache(in = xbar.io.out, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, enable = true)(CacheConfig(ro = false, name = "l2cache", cacheLevel = 2))
31    io.mem <> l2cacheOut.toAXI4()
32  } else {
33    io.mem <> xbar.io.out.toAXI4()
34  }
35
36  noop.io.imem.coh.resp.ready := true.B
37  noop.io.imem.coh.req.valid := false.B
38  noop.io.imem.coh.req.bits := DontCare
39
40  if (p.FPGAPlatform) io.mmio <> noop.io.mmio.toAXI4Lite()
41  else io.mmio <> noop.io.mmio
42
43  val mtipSync = RegNext(RegNext(io.mtip))
44  val meipSync = RegNext(RegNext(io.meip))
45  BoringUtils.addSource(mtipSync, "mtip")
46  BoringUtils.addSource(meipSync, "meip")
47}
48