xref: /XiangShan/src/main/scala/system/SoC.scala (revision 5704b623ceb4fd3ffad4b285e8aab19175f40feb) 
1package system
2
3import noop.{NOOP, NOOPConfig, Cache, L2Cache, CacheConfig}
4import bus.axi4.{AXI4, AXI4Lite}
5import bus.simplebus._
6
7import chisel3._
8import chisel3.util.experimental.BoringUtils
9
10class NOOPSoC(implicit val p: NOOPConfig) extends Module {
11  val io = IO(new Bundle{
12    val mem = new AXI4
13    val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
14    val mtip = Input(Bool())
15    val meip = Input(Bool())
16  })
17
18  val noop = Module(new NOOP)
19  val cohMg = Module(new CoherenceInterconnect)
20  cohMg.io.in(0) <> noop.io.imem
21  cohMg.io.in(1) <> noop.io.dmem
22  // io.mem <> cohMg.io.out.toAXI4()
23	val mmioXbar = Module(new SimpleBusCrossbarNto1(2))
24
25	val l2cacheOut = Wire(new SimpleBusUC)
26	l2cacheOut <> Cache(in = cohMg.io.out, mmio = mmioXbar.io.in(0), flush = "b00".U, enable = true)(CacheConfig(ro = false, name = "l2cache", cacheLevel = 2))
27	io.mem <> l2cacheOut.toAXI4()
28	/*
29	val l2cache = Module(new L2Cache)
30	l2cache.io.in <> cohMg.io.out
31	mmioXbar.io.in(0) <> l2cache.io.mmio
32	l2cache.io.flush := "b00".U
33	io.mem <> l2cache.io.out.toAXI4()
34	*/
35
36	mmioXbar.io.in(1) <> noop.io.mmio
37	if (p.FPGAPlatform) io.mmio <> mmioXbar.io.out.toAXI4Lite()
38  else io.mmio <> mmioXbar.io.out
39	/*
40  if (p.FPGAPlatform) io.mmio <> noop.io.mmio.toAXI4Lite()
41  else io.mmio <> noop.io.mmio
42	*/
43  val mtipSync = RegNext(RegNext(io.mtip))
44  val meipSync = RegNext(RegNext(io.meip))
45  BoringUtils.addSource(mtipSync, "mtip")
46  BoringUtils.addSource(meipSync, "meip")
47}
48