xref: /XiangShan/src/main/scala/system/SoC.scala (revision 096ea47e5e91ada5b956e733200b9e1797ccd9aa) 
1package system
2
3import noop.{NOOP, NOOPConfig, Cache, L2Cache, CacheConfig}
4import bus.axi4.{AXI4, AXI4Lite}
5import bus.simplebus._
6
7import chisel3._
8import chisel3.util._
9import chisel3.util.experimental.BoringUtils
10
11class NOOPSoC(implicit val p: NOOPConfig) extends Module {
12  val io = IO(new Bundle{
13    val mem = new AXI4
14    val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
15    val mtip = Input(Bool())
16    val meip = Input(Bool())
17  })
18
19  val noop = Module(new NOOP)
20  val cohMg = Module(new CoherenceInterconnect)
21  cohMg.io.in(0) <> noop.io.imem
22  cohMg.io.in(1) <> noop.io.dmem
23
24	/*
25	// add L2 Cache and Dcache Prefetcher
26	val prefetcher = Module(new Prefetcher)
27	prefetcher.io.in <> noop.io.prefetchReq
28
29	val l2cacheIn = Wire(new SimpleBusUC)
30	val l2cacheInReqArb = Module(new Arbiter(noop.io.prefetchReq, 2))
31	l2cacheInReqArb.io.in(0) <> cohMg.io.out.req
32	l2cacheInReqArb.io.in(1) <> prefetcher.io.out
33	l2cacheIn.req <> l2cacheInReqArb.io.out
34	cohMg.io.out.resp <> l2cacheIn.resp
35
36	val mmioXbar = Module(new SimpleBusCrossbarNto1(2))
37
38	val l2cacheOut = Wire(new SimpleBusUC)
39	l2cacheOut <> Cache(in = l2cacheIn, mmio = mmioXbar.io.in(0), flush = "b00".U, enable = true)(CacheConfig(ro = false, name = "l2cache", cacheLevel = 2))
40	io.mem <> l2cacheOut.toAXI4()
41
42	mmioXbar.io.in(1) <> noop.io.mmio
43	if (p.FPGAPlatform) io.mmio <> mmioXbar.io.out.toAXI4Lite()
44  else io.mmio <> mmioXbar.io.out
45	*/
46
47	// add L2 Cache
48	val mmioXbar = Module(new SimpleBusCrossbarNto1(2))
49
50	val l2cacheOut = Wire(new SimpleBusUC)
51	l2cacheOut <> Cache(in = cohMg.io.out, mmio = mmioXbar.io.in(0), flush = "b00".U, enable = true)(CacheConfig(ro = false, name = "l2cache", cacheLevel = 2))
52	io.mem <> l2cacheOut.toAXI4()
53
54	mmioXbar.io.in(1) <> noop.io.mmio
55	if (p.FPGAPlatform) io.mmio <> mmioXbar.io.out.toAXI4Lite()
56  else io.mmio <> mmioXbar.io.out
57
58	/*
59	// no L2 Cache
60	io.mem <> cohMg.io.out.toAXI4()
61
62  if (p.FPGAPlatform) io.mmio <> noop.io.mmio.toAXI4Lite()
63  else io.mmio <> noop.io.mmio
64	*/
65  val mtipSync = RegNext(RegNext(io.mtip))
66  val meipSync = RegNext(RegNext(io.meip))
67  BoringUtils.addSource(mtipSync, "mtip")
68  BoringUtils.addSource(meipSync, "meip")
69}
70