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/nrf52832-nimble/nordic/nrfx/mdk/
H A Dnrf51.svd121 <name>Disabled</name>
122 <description>Interrupt disabled.</description>
154 <name>Disabled</name>
155 <description>Interrupt disabled.</description>
412 <name>Disabled</name>
413 <description>Disabled.</description>
554 <name>Disabled</name>
555 <description>Pin reset in debug interface mode disabled.</description>
656 <name>Disabled</name>
657 <description>DCDC converter disabled.</description>
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H A Dnrf52.svd941 <name>Disabled</name>
968 <name>Disabled</name>
1008 <name>Disabled</name>
1009 <description>Protection disabled</description>
1026 <name>Disabled</name>
1027 <description>Protection disabled</description>
1044 <name>Disabled</name>
1045 <description>Protection disabled</description>
1062 <name>Disabled</name>
1063 <description>Protection disabled</description>
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H A Dnrf52810.svd786 <name>Disabled</name>
826 <name>Disabled</name>
827 <description>Protection disabled</description>
844 <name>Disabled</name>
845 <description>Protection disabled</description>
862 <name>Disabled</name>
863 <description>Protection disabled</description>
880 <name>Disabled</name>
881 <description>Protection disabled</description>
898 <name>Disabled</name>
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H A Dnrf51_bitfields.h47 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
54 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
61 #define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
71 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
78 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
85 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
102 #define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
118 #define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
131 #define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
141 #define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
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H A Dnrf52840.svd1115 <name>Disabled</name>
1142 <name>Disabled</name>
1174 <name>Disabled</name>
1192 <name>Disabled</name>
1453 <name>Disabled</name>
1454 <description>Read: Disabled</description>
1480 <name>Disabled</name>
1481 <description>Read: Disabled</description>
1507 <name>Disabled</name>
1508 <description>Read: Disabled</description>
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H A Dnrf52_bitfields.h47 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
54 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
61 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
71 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
78 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
85 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
143 #define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
149 #define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
155 #define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
161 #define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
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H A Dnrf9160.svd675 <name>Disabled</name>
693 <name>Disabled</name>
711 <name>Disabled</name>
799 <name>DISABLED</name>
1138 <name>Disabled</name>
1169 <name>Disabled</name>
1200 <name>Disabled</name>
1226 <name>Disabled</name>
1244 <name>Disabled</name>
1262 <name>Disabled</name>
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H A Dnrf52810_bitfields.h82 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
89 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
96 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
106 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
113 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
120 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
178 #define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
184 #define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
190 #define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
196 #define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
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H A Dnrf52840_bitfields.h82 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
89 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
96 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
106 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
113 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
120 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
269 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
276 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
283 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
293 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
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H A Dnrf9160_bitfields.h190 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
197 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
207 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
214 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
311 #define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled */
517 #define DPPIC_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
524 #define DPPIC_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
531 #define DPPIC_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
538 #define DPPIC_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
545 #define DPPIC_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
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/nrf52832-nimble/rt-thread/libcpu/arm/s3c44b0/
H A Dstart_rvds.S27 I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
28 F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
603 ;// <o2.0> PC0 Pull-up <0=> Enabled <1=> Disabled
604 ;// <o2.1> PC1 Pull-up <0=> Enabled <1=> Disabled
605 ;// <o2.2> PC2 Pull-up <0=> Enabled <1=> Disabled
606 ;// <o2.3> PC3 Pull-up <0=> Enabled <1=> Disabled
607 ;// <o2.4> PC4 Pull-up <0=> Enabled <1=> Disabled
608 ;// <o2.5> PC5 Pull-up <0=> Enabled <1=> Disabled
609 ;// <o2.6> PC6 Pull-up <0=> Enabled <1=> Disabled
610 ;// <o2.7> PC7 Pull-up <0=> Enabled <1=> Disabled
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/nrf52832-nimble/rt-thread/components/dfs/filesystems/jffs2/src/
H A Dcompr.c71 /* Skip decompress-only backwards-compatibility and disabled modules */ in jffs2_compress()
72 if ((!this->compress)||(this->disabled)) in jffs2_compress()
98 /* Skip decompress-only backwards-compatibility and disabled modules */ in jffs2_compress()
99 if ((!this->compress)||(this->disabled)) in jffs2_compress()
283 if ((this->disabled)||(!this->compress)) in jffs2_list_compressors()
284 act_buf += sprintf(act_buf,"disabled"); in jffs2_list_compressors()
306 if ((this->disabled)||(!this->compress)) in jffs2_stats()
350 static int jffs2_compressor_Xable(const char *name, int disabled) in jffs2_compressor_Xable() argument
356 this->disabled = disabled; in jffs2_compressor_Xable()
H A Dcompr_rtime.c119 .disabled = 1,
121 .disabled = 0,
134 1,//.disabled =
136 0,//.disabled =
H A Dcompr_zlib.c198 .disabled = 1,
200 .disabled = 0,
213 1,//.disabled =
215 0,//.disabled =
/nrf52832-nimble/nordic/nrfx/drivers/include/
H A Dnrfx_dppi.h87 * @param[in] channel DPPI channel to be disabled.
89 * @retval NRFX_SUCCESS If the channel was successfully disabled.
163 * @param[in] group Channel group to be disabled.
165 * @retval NRFX_SUCCESS If the group was successfully disabled.
H A Dnrfx_ppi.h135 * @param[in] channel PPI channel to be disabled.
137 * @retval NRFX_SUCCESS If the channel was successfully disabled.
139 * @retval NRFX_ERROR_INVALID_PARAM If the channel cannot be disabled by the user.
267 * @param[in] group Channel group to be disabled.
269 * @retval NRFX_SUCCESS If the group was successfully disabled.
H A Dnrfx_power.h143 * The regulator would be enabled or disabled automatically
154 * The regulator would be enabled or disabled automatically
247 * If event handler is set to NULL, interrupt would be disabled.
255 * would be disabled.
/nrf52832-nimble/rt-thread/components/net/freemodbus/modbus/include/
H A Dmb_m.h101 * note that the receiver is still disabled and no Modbus frames are
112 * The protocol is then in the disabled state and ready for activation
124 * frame processing is still disabled until eMBEnable( ) is called.
141 * is disabled.
147 * If the protocol stack is not in the disabled state it returns
156 * stack is only possible if it is in the disabled state.
159 * eMBErrorCode::MB_ENOERR. If it was not in the disabled state it
169 * \return If the protocol stack has been disabled it returns
H A Dmb.h131 * note that the receiver is still disabled and no Modbus frames are
144 * The protocol is then in the disabled state and ready for activation
158 * frame processing is still disabled until eMBEnable( ) is called.
175 * is disabled.
181 * If the protocol stack is not in the disabled state it returns
190 * stack is only possible if it is in the disabled state.
193 * eMBErrorCode::MB_ENOERR. If it was not in the disabled state it
203 * \return If the protocol stack has been disabled it returns
/nrf52832-nimble/rt-thread/components/lwp/arch/arm/cortex-a9/
H A Dlwp_gcc.S21 #define I_Bit 0x80 @; when I bit is set, IRQ is disabled
22 #define F_Bit 0x40 @; when F bit is set, FIQ is disabled
/nrf52832-nimble/rt-thread/components/lwp/arch/arm/arm9/
H A Dlwp_gcc.S21 #define I_Bit 0x80 @; when I bit is set, IRQ is disabled
22 #define F_Bit 0x40 @; when F bit is set, FIQ is disabled
/nrf52832-nimble/packages/NimBLE-latest/nimble/controller/include/controller/
H A Dble_ll_hci.h45 /* Used to determine if the LE event is enabled/disabled */
48 /* Used to determine if event is enabled/disabled */
/nrf52832-nimble/rt-thread/components/vmm/
H A Dvmm_context.c29 /* When loading RT-Thread, the IRQ on the guest should be disabled. */ in vmm_context_init()
256 vmm_info("VMM WARING: IRQ disabled in guest\n"); in vmm_verify_guest_status()
262 vmm_info("VMM WARING: FIQ disabled in guest\n"); in vmm_verify_guest_status()
270 vmm_info("VMM WARING: VIRQ disabled in user mode\n"); in vmm_verify_guest_status()
/nrf52832-nimble/packages/NimBLE-latest/docs/ble_setup/
H A Dble_lp_clock.rst25 - Default 1 MHz clock source can be disabled if not used by application
30 Hz clock. Also, timer 0 can be disabled since this is the default source
/nrf52832-nimble/packages/NimBLE-latest/nimble/drivers/nrf52/src/
H A Dble_phy.c51 * - CH19 = (optional) gpio debug for wfr timer radio disabled
210 * serviced the radio interrupt (interrupts were disabled).
695 /* Enable the disabled interrupt so we time out on events compare */ in ble_phy_wfr_enable()
854 /* Clear events and clear interrupt on disabled event */ in ble_phy_tx_end_isr()
1082 /* Clear wfr timer channels and DISABLED interrupt */ in ble_phy_rx_start_isr()
1136 * If state is disabled, we should have the BCMATCH. If not, in ble_phy_rx_start_isr()
1206 * we have both an ADDRESS and DISABLED interrupt in rx state. If we get in ble_phy_isr()
1207 * an address, we disable the DISABLED interrupt. in ble_phy_isr()
1216 * be disabled while we are waiting for EVENT_BCCMATCH after 1st byte in ble_phy_isr()
1218 * case we should not clear DISABLED irq mask so it will be handled as in ble_phy_isr()
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