Lines Matching full:disabled

82 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
89 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
96 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
106 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
113 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
120 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
178 #define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
184 #define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
190 #define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
196 #define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
202 #define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
208 #define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
214 #define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
220 #define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
226 #define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
232 #define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
238 #define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
244 #define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
250 #define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
256 #define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
262 #define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
268 #define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
274 #define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
280 #define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
286 #define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
292 #define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
298 #define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
304 #define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
310 #define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
316 #define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
322 #define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
328 #define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
334 #define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
340 #define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
346 #define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
352 #define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
358 #define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
364 #define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
373 #define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
379 #define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
385 #define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
391 #define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
397 #define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
403 #define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
409 #define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
415 #define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
421 #define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
427 #define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
433 #define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
439 #define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
445 #define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
451 #define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
457 #define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
463 #define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
473 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disabled in debug */
543 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
550 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
557 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
567 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
574 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
581 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
760 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
767 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
774 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
781 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
791 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
798 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
805 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
812 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1023 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
1030 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
1037 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
1044 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
1054 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
1061 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
1068 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
1075 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
1172 #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
1213 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1220 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1230 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1237 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1371 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1378 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1385 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1392 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1399 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1406 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1413 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1420 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1427 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1434 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1441 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1448 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1455 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1462 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1469 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1476 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1486 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1493 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1500 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1507 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1514 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1521 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1528 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1535 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1542 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1549 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1556 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1563 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1570 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1577 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1584 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1591 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1867 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
1874 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
1881 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
1888 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
1895 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
1902 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
1909 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
1916 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
1923 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
1933 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
1940 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
1947 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
1954 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
1961 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
1968 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
1975 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
1982 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
1989 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
2017 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired…
3804 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
3905 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
3912 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
3919 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
3929 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
3936 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
3943 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
4086 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
4093 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
4100 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
4110 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
4117 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
4124 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
4515 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
4522 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
4529 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
4536 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
4543 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
4550 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
4557 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
4564 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
4571 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
4578 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
4585 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
4592 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
4599 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
4606 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
4613 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
4620 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
4627 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
4634 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
4641 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
4648 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
4655 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
4662 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
4669 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
4676 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
4683 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
4690 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
4697 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
4704 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
4711 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
4718 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
4725 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
4732 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
4742 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
4749 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
4756 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
4763 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
4770 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
4777 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
4784 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
4791 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
4798 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
4805 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
4812 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
4819 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
4826 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
4833 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
4840 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
4847 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
4854 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
4861 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
4868 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
4875 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
4882 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
4889 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
4896 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
4903 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
4910 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
4917 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
4924 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
4931 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
4938 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
4945 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
4952 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
4959 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
5323 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
5330 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
5337 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
5344 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
5351 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
5358 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
5365 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5375 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
5382 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
5389 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
5396 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
5403 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
5410 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
5417 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5427 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
5484 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
5499 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is…
5654 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5661 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
5668 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
5675 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
5682 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
5692 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5699 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
5706 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
5713 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
5720 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
5842 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
5962 /* Description: RADIO has been disabled */
6013 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */
6037 /* Bit 3 : Shortcut between DISABLED event and RXEN task */
6043 /* Bit 2 : Shortcut between DISABLED event and TXEN task */
6067 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
6074 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
6081 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
6088 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
6095 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
6102 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
6106 /* Bit 4 : Write '1' to enable interrupt for DISABLED event */
6107 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
6108 …IO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
6109 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
6116 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6123 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
6130 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
6137 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
6147 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
6154 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
6161 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
6168 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
6175 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
6182 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
6186 /* Bit 4 : Write '1' to disable interrupt for DISABLED event */
6187 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
6188 …IO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
6189 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
6196 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
6203 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
6210 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
6217 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
6475 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
6514 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
6590 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
6596 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
6602 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
6608 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
6614 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
6620 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
6626 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
6632 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
6700 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
6710 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
6720 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
6789 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
6796 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
6803 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
6810 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
6817 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
6824 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
6834 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
6841 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
6848 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
6855 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
6862 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
6869 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
6918 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
6925 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
6932 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
6939 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
6946 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
6953 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
6963 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
6970 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
6977 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
6984 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
6991 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
6998 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
7252 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
7259 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
7266 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
7273 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
7280 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
7287 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
7294 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
7301 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
7308 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
7315 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
7322 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
7329 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
7336 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
7343 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
7350 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
7357 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
7364 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7371 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
7378 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
7385 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
7392 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
7399 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
7409 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
7416 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
7423 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
7430 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
7437 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
7444 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
7451 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
7458 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
7465 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
7472 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
7479 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
7486 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
7493 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
7500 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
7507 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
7514 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
7521 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7528 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
7535 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
7542 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
7549 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
7556 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
7618 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
7825 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
7832 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
7839 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
7846 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7853 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7863 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
7870 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
7877 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
7884 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7891 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8099 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
8106 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
8113 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
8123 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
8130 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
8137 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
8338 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
8348 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
8612 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
8619 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
8626 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8633 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8640 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8647 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8657 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
8664 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
8671 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8678 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8685 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8692 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8909 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
8916 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
8923 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
8930 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
8937 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
8944 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
8951 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8961 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
8968 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
8975 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
8982 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
8989 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
8996 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9003 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9281 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
9288 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
9295 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9302 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9309 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
9316 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9326 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
9333 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
9340 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9347 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9354 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9361 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9483 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
9489 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
9705 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
9712 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9719 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9726 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
9733 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
9740 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
9747 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
9754 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
9761 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
9768 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
9775 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
9785 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
9792 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9799 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9806 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
9813 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9820 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
9827 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
9834 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
9841 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
9848 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
9855 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
10032 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
10106 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
10116 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */