Lines Matching full:disabled

47 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
54 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
61 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
71 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
78 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
85 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
143 #define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
149 #define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
155 #define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
161 #define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
167 #define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
173 #define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
179 #define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
185 #define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
191 #define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
197 #define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
203 #define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
209 #define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
215 #define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
221 #define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
227 #define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
233 #define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
239 #define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
245 #define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
251 #define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
257 #define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
263 #define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
269 #define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
275 #define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
281 #define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
287 #define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
293 #define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
299 #define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
305 #define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
311 #define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
317 #define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
323 #define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
329 #define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
338 #define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */
344 #define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */
350 #define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */
356 #define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */
362 #define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */
368 #define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */
374 #define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */
380 #define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */
386 #define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */
392 #define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */
398 #define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */
404 #define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */
410 #define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */
416 #define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */
422 #define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */
428 #define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */
434 #define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
440 #define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
446 #define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
452 #define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
458 #define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
464 #define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
470 #define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
476 #define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
482 #define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
488 #define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
494 #define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
500 #define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
506 #define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
512 #define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
518 #define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
524 #define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
542 #define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */
548 #define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */
554 #define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */
560 #define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */
566 #define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */
572 #define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */
578 #define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */
584 #define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */
590 #define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */
596 #define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */
602 #define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */
608 #define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */
614 #define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */
620 #define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */
626 #define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */
632 #define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */
638 #define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */
644 #define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */
650 #define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */
656 #define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */
662 #define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */
668 #define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */
674 #define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */
680 #define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */
686 #define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */
692 #define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */
698 #define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */
704 #define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */
710 #define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */
716 #define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */
722 #define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */
728 #define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */
737 #define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */
743 #define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */
749 #define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */
755 #define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */
761 #define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */
767 #define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */
773 #define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */
779 #define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */
785 #define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */
791 #define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */
797 #define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */
803 #define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */
809 #define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */
815 #define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */
821 #define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */
827 #define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */
833 #define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */
839 #define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */
845 #define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */
851 #define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */
857 #define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */
863 #define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */
869 #define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */
875 #define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */
881 #define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */
887 #define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */
893 #define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */
899 #define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */
905 #define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */
911 #define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */
917 #define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */
923 #define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */
945 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
952 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
959 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
969 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
976 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
983 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
1064 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
1071 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
1078 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1085 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1095 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
1102 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
1109 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1116 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1296 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
1303 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
1310 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
1317 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
1327 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
1334 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
1341 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
1348 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
1445 #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
1454 #define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
1469 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1476 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1486 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1493 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1613 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1620 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1627 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1634 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1641 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1648 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1655 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1662 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1669 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1676 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1683 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1690 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1697 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1704 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1711 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1718 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1728 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1735 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1742 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1749 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1756 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1763 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1770 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1777 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1784 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1791 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1798 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1805 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1812 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1819 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1826 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1833 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
2154 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
2161 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
2168 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
2175 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
2182 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
2189 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
2196 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
2203 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
2210 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
2220 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
2227 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
2234 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
2241 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
2248 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
2255 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
2262 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
2269 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
2276 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
2304 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired…
2339 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2346 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2353 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2363 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2370 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2377 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2405 #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to…
2414 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read fr…
2423 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not…
2634 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
2641 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
2648 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
2655 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
2665 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
2672 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
2679 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
2686 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
2771 #define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
2772 #define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
2859 #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2866 #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2873 #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2880 #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2887 #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2894 #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2901 #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
2908 #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
2915 #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
2922 #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
2929 #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
2936 #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
2946 #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2953 #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2960 #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2967 #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2974 #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2981 #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2988 #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
2995 #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3002 #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3009 #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3016 #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3023 #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3108 #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3115 #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3122 #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3129 #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3136 #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3143 #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3150 #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3157 #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3164 #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3171 #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3178 #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3185 #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3195 #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3202 #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3209 #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3216 #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3223 #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3230 #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3237 #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3244 #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3251 #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3258 #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3265 #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3272 #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3747 #define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3754 #define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled …
3761 #define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3768 #define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled …
3775 #define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3782 #define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3789 #define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3796 #define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3803 #define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3810 #define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3817 #define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3824 #define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3834 #define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3841 #define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled …
3848 #define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3855 #define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled …
3862 #define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3869 #define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3876 #define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3883 #define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3890 #define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3897 #define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3904 #define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3911 #define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
4256 #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
4263 #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4270 #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4277 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4284 #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4291 #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4298 #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4305 #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
4312 #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4319 #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4326 #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4333 #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4340 #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4347 #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4354 #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
4364 #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
4371 #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4378 #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4385 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4392 #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4399 #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4406 #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4413 #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
4420 #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4427 #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4434 #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4441 #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4448 #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4455 #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4462 #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
6537 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
6603 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6610 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6617 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
6627 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
6634 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6641 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
6749 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
6756 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
6763 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
6773 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
6780 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
6787 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
7257 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
7264 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
7271 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
7278 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
7285 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
7292 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
7299 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
7306 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
7313 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
7320 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
7327 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
7334 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
7341 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
7348 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
7355 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
7362 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
7369 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
7376 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
7383 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
7390 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
7397 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
7404 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
7411 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
7418 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
7425 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
7432 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
7439 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
7446 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
7453 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
7460 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
7467 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
7474 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
7484 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
7491 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
7498 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
7505 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
7512 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
7519 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
7526 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
7533 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
7540 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
7547 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
7554 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
7561 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
7568 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
7575 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
7582 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
7589 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
7596 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
7603 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
7610 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
7617 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
7624 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
7631 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
7638 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
7645 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
7652 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
7659 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
7666 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
7673 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
7680 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
7687 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
7694 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
7701 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
8009 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
8016 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
8023 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
8030 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
8037 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
8044 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
8051 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8061 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
8068 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
8075 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
8082 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
8089 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
8096 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
8103 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8113 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
8170 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
8185 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is…
8270 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8277 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
8284 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
8291 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
8298 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
8308 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8315 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
8322 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
8329 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
8336 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
8458 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
8489 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */
8513 /* Bit 3 : Shortcut between DISABLED event and RXEN task */
8519 /* Bit 2 : Shortcut between DISABLED event and TXEN task */
8543 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
8550 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
8557 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
8564 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
8571 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
8578 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
8582 /* Bit 4 : Write '1' to Enable interrupt for DISABLED event */
8583 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
8584 …IO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
8585 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
8592 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
8599 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
8606 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
8613 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
8623 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
8630 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
8637 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
8644 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
8651 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
8658 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
8662 /* Bit 4 : Write '1' to Disable interrupt for DISABLED event */
8663 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
8664 …IO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
8665 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
8672 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
8679 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
8686 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
8693 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
8952 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
8991 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
9067 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
9073 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
9079 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
9085 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
9091 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
9097 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
9103 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
9109 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
9156 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
9166 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
9176 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
9196 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9203 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9210 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9217 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9224 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
9231 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
9241 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9248 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9255 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9262 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9269 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
9276 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
9325 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9332 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9339 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9346 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9353 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
9360 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
9370 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9377 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9384 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9391 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9398 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
9405 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
9575 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
9582 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
9589 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
9596 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
9603 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
9610 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
9617 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
9624 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
9631 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
9638 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
9645 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
9652 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
9659 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
9666 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
9673 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
9680 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
9687 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9694 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
9701 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
9708 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
9715 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
9722 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
9732 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
9739 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
9746 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
9753 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
9760 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
9767 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
9774 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
9781 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
9788 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
9795 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
9802 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
9809 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
9816 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
9823 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
9830 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
9837 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
9844 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9851 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
9858 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
9865 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
9872 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
9879 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
9941 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
10076 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
10086 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
10191 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
10198 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10205 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
10212 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10219 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
10229 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
10236 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10243 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
10250 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10257 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
10430 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
10437 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10444 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
10454 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
10461 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10468 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
10648 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
10658 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
10873 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
10880 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
10887 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
10894 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
10901 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
10908 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
10918 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
10925 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
10932 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
10939 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
10946 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
10953 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11017 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
11024 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
11031 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11038 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
11045 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
11052 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11062 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
11069 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
11076 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
11083 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
11090 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
11097 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11269 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
11276 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
11283 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11290 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11297 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
11304 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11311 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11321 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
11328 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
11335 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11342 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11349 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
11356 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
11363 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11564 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
11571 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
11578 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11585 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11592 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11599 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11609 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
11616 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
11623 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11630 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11637 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
11644 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11766 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
11772 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
11807 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
11814 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11821 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
11828 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
11835 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
11842 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
11852 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
11859 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
11866 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
11873 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
11880 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
11887 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
12010 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
12107 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
12114 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12121 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12128 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
12135 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
12142 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12149 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
12156 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12163 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
12170 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
12177 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
12187 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
12194 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12201 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12208 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
12215 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
12222 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12229 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
12236 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12243 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
12250 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
12257 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
12428 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
12497 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
12507 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */