1*10465441SEvalZero/* 2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team 3*10465441SEvalZero * 4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0 5*10465441SEvalZero * 6*10465441SEvalZero * Change Logs: 7*10465441SEvalZero * Date Author Notes 8*10465441SEvalZero * 2018-12-10 Jesven first version 9*10465441SEvalZero */ 10*10465441SEvalZero 11*10465441SEvalZero#define Mode_USR 0x10 12*10465441SEvalZero#define Mode_FIQ 0x11 13*10465441SEvalZero#define Mode_IRQ 0x12 14*10465441SEvalZero#define Mode_SVC 0x13 15*10465441SEvalZero#define Mode_MON 0x16 16*10465441SEvalZero#define Mode_ABT 0x17 17*10465441SEvalZero#define Mode_UDF 0x1B 18*10465441SEvalZero#define Mode_SYS 0x1F 19*10465441SEvalZero 20*10465441SEvalZero#define A_Bit 0x100 21*10465441SEvalZero#define I_Bit 0x80 @; when I bit is set, IRQ is disabled 22*10465441SEvalZero#define F_Bit 0x40 @; when F bit is set, FIQ is disabled 23*10465441SEvalZero#define T_Bit 0x20 24*10465441SEvalZero 25*10465441SEvalZero.cpu arm9 26*10465441SEvalZero.syntax unified 27*10465441SEvalZero.text 28*10465441SEvalZero 29*10465441SEvalZero/* 30*10465441SEvalZero * void lwp_user_entry(args, text, data); 31*10465441SEvalZero */ 32*10465441SEvalZero.global lwp_user_entry 33*10465441SEvalZero.type lwp_user_entry, % function 34*10465441SEvalZerolwp_user_entry: 35*10465441SEvalZero mrs r9, cpsr 36*10465441SEvalZero mov r8, r9 37*10465441SEvalZero bic r9, #0x1f 38*10465441SEvalZero orr r9, #Mode_USR 39*10465441SEvalZero 40*10465441SEvalZero orr r8, #I_Bit 41*10465441SEvalZero msr cpsr_c, r8 42*10465441SEvalZero 43*10465441SEvalZero msr spsr, r9 44*10465441SEvalZero 45*10465441SEvalZero /* set data address. */ 46*10465441SEvalZero mov r9, r2 47*10465441SEvalZero movs pc, r1 48*10465441SEvalZero 49*10465441SEvalZero/* 50*10465441SEvalZero * void SVC_Handler(void); 51*10465441SEvalZero */ 52*10465441SEvalZero.global SVC_Handler 53*10465441SEvalZero.type SVC_Handler, % function 54*10465441SEvalZeroSVC_Handler: 55*10465441SEvalZero push {lr} 56*10465441SEvalZero mrs lr, spsr 57*10465441SEvalZero push {r4, r5, lr} 58*10465441SEvalZero 59*10465441SEvalZero mrs r4, cpsr 60*10465441SEvalZero bic r4, #I_Bit 61*10465441SEvalZero msr cpsr_c, r4 62*10465441SEvalZero 63*10465441SEvalZero push {r0 - r3, r12} 64*10465441SEvalZero and r0, r7, #0xff 65*10465441SEvalZero bl lwp_get_sys_api 66*10465441SEvalZero cmp r0, #0 /* r0 = api */ 67*10465441SEvalZero mov r4, r0 68*10465441SEvalZero pop {r0 - r3, r12} 69*10465441SEvalZero beq svc_exit 70*10465441SEvalZero ldr lr, = svc_exit 71*10465441SEvalZero bx r4 72*10465441SEvalZero 73*10465441SEvalZerosvc_exit: 74*10465441SEvalZero mrs r4, cpsr 75*10465441SEvalZero orr r4, #I_Bit 76*10465441SEvalZero msr cpsr_c, r4 77*10465441SEvalZero 78*10465441SEvalZero pop {r4, r5, lr} 79*10465441SEvalZero msr spsr_cxsf, lr 80*10465441SEvalZero pop {lr} 81*10465441SEvalZero movs pc, lr 82