Lines Matching full:disabled

82 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
89 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
96 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
106 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
113 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
120 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
269 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
276 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
283 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
293 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
300 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
307 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
566 #define CLOCK_INTENSET_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */
573 #define CLOCK_INTENSET_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */
580 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
587 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
594 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
601 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
611 #define CLOCK_INTENCLR_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */
618 #define CLOCK_INTENCLR_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */
625 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
632 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
639 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
646 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
899 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
906 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
913 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
920 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
930 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
937 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
944 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
951 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
1048 #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
1061 #define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled */
1102 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1109 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1119 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1126 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1260 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1267 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1274 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1281 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1288 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1295 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1302 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1309 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1316 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1323 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1330 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1337 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1344 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1351 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1358 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1365 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1375 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1382 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1389 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1396 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1403 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1410 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1417 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1424 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1431 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1438 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1445 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1452 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1459 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1466 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1473 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1480 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1903 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
1910 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
1917 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
1924 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
1931 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
1938 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
1945 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
1952 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
1959 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
1969 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
1976 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
1983 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
1990 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
1997 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
2004 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
2011 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
2018 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
2025 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
2057 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired…
2129 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2136 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2143 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2153 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2160 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2167 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2195 #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to…
2204 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read fr…
2213 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not…
2493 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
2500 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
2507 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
2514 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
2524 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
2531 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
2538 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
2545 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
2630 #define LPCOMP_HYST_HYST_Disabled (0UL) /*!< Comparator hysteresis disabled */
2746 #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2753 #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2760 #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2767 #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2774 #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2781 #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2788 #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
2795 #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
2802 #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
2809 #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
2816 #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
2823 #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
2833 #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2840 #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2847 #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2854 #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2861 #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2868 #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2875 #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
2882 #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
2889 #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
2896 #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
2903 #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
2910 #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
2995 #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3002 #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3009 #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3016 #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3023 #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3030 #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3037 #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3044 #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3051 #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3058 #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3065 #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3072 #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3082 #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3089 #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3096 #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3103 #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3110 #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3117 #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3124 #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3131 #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3138 #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3145 #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3152 #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3159 #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3634 #define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3641 #define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled …
3648 #define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3655 #define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled …
3662 #define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3669 #define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3676 #define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3683 #define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3690 #define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3697 #define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3704 #define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3711 #define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3721 #define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3728 #define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled …
3735 #define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3742 #define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled …
3749 #define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3756 #define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3763 #define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3770 #define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3777 #define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3784 #define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3791 #define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3798 #define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
4303 #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
4310 #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4317 #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4324 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4331 #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4338 #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4345 #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4352 #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
4359 #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4366 #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4373 #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4380 #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4387 #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4394 #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4401 #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
4411 #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
4418 #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4425 #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4432 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4439 #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4446 #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4453 #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4460 #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
4467 #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4474 #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4481 #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4488 #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4495 #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4502 #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4509 #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
4547 #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Disabled (0UL) /*!< Disabled or sense */
4745 #define NFCT_AUTOCOLRESCONFIG_MODE_Disabled (1UL) /*!< Auto collision resolution disabled */
6623 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
6724 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6731 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6738 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
6748 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
6755 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6762 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
6946 #define POWER_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
6953 #define POWER_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
6960 #define POWER_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
6967 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
6974 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
6981 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
6991 #define POWER_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */
6998 #define POWER_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */
7005 #define POWER_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */
7012 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
7019 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
7026 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
7963 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
7970 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
7977 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
7984 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
7991 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
7998 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
8005 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
8012 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
8019 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
8026 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
8033 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
8040 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
8047 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
8054 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
8061 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
8068 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
8075 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
8082 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
8089 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
8096 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
8103 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
8110 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
8117 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
8124 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
8131 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
8138 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
8145 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
8152 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
8159 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
8166 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
8173 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
8180 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
8190 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
8197 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
8204 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
8211 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
8218 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
8225 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
8232 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
8239 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
8246 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
8253 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
8260 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
8267 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
8274 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
8281 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
8288 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
8295 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
8302 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
8309 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
8316 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
8323 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
8330 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
8337 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
8344 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
8351 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
8358 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
8365 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
8372 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
8379 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
8386 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
8393 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
8400 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
8407 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
8771 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
8778 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
8785 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
8792 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
8799 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
8806 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
8813 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8823 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
8830 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
8837 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
8844 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
8851 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
8858 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
8865 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8875 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
8932 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
8947 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is…
9106 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9113 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
9120 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
9127 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
9134 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
9144 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9151 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
9158 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
9165 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
9172 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
9306 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
9391 #define QSPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
9401 #define QSPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
9719 #define QSPI_CINSTRCONF_LFEN_Disable (0UL) /*!< Long frame mode disabled */
9928 /* Description: RADIO has been disabled */
10122 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */
10146 /* Bit 3 : Shortcut between DISABLED event and RXEN task */
10152 /* Bit 2 : Shortcut between DISABLED event and TXEN task */
10176 #define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */
10183 #define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
10190 #define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */
10197 #define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */
10204 #define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
10211 #define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
10218 #define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
10225 #define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
10232 #define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10239 #define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */
10246 #define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
10253 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
10260 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
10267 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
10274 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
10281 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
10288 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
10292 /* Bit 4 : Write '1' to enable interrupt for DISABLED event */
10293 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
10294 …IO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
10295 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
10302 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
10309 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
10316 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
10323 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
10333 #define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */
10340 #define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */
10347 #define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */
10354 #define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */
10361 #define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */
10368 #define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */
10375 #define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */
10382 #define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */
10389 #define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10396 #define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */
10403 #define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */
10410 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
10417 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
10424 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
10431 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
10438 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
10445 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
10449 /* Bit 4 : Write '1' to disable interrupt for DISABLED event */
10450 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
10451 …IO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
10452 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
10459 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
10466 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
10473 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
10480 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
10778 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
10817 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
10893 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
10899 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
10905 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
10911 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
10917 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
10923 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
10929 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
10935 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
11048 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
11058 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
11068 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
11137 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11144 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11151 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11158 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11165 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11172 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
11182 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11189 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11196 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11203 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11210 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11217 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
11266 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11273 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11280 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11287 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11294 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11301 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
11311 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
11318 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
11325 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
11332 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
11339 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
11346 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
11600 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
11607 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
11614 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
11621 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
11628 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
11635 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
11642 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
11649 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
11656 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
11663 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
11670 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
11677 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
11684 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
11691 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
11698 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
11705 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
11712 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11719 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
11726 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
11733 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
11740 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
11747 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
11757 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
11764 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
11771 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
11778 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
11785 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
11792 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
11799 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
11806 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
11813 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
11820 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
11827 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
11834 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
11841 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
11848 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
11855 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
11862 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
11869 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11876 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
11883 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
11890 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
11897 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
11904 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
11968 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
12110 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
12120 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
12315 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
12322 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12329 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
12336 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12343 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12353 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
12360 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12367 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
12374 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12381 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
12682 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
12689 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12696 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
12706 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
12713 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12720 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
12937 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
12947 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
13211 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
13218 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
13225 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
13232 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
13239 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
13246 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
13256 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
13263 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
13270 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
13277 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
13284 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
13291 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
13432 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
13439 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
13446 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
13453 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
13460 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
13467 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
13477 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
13484 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
13491 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
13498 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
13505 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
13512 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
13789 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
13796 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
13803 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13810 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13817 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
13824 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
13831 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
13841 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
13848 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
13855 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13862 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
13869 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
13876 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
13883 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
14169 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
14176 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
14183 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14190 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14197 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
14204 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
14214 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
14221 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
14228 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14235 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14242 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
14249 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
14379 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
14385 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
14497 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
14504 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
14511 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
14518 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
14525 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
14532 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
14542 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
14549 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
14556 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
14563 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
14570 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
14577 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
14736 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
14945 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
14952 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14959 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
14966 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
14973 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
14980 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
14987 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
14994 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
15001 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
15008 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
15015 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
15025 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
15032 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
15039 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
15046 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
15053 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
15060 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
15067 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
15074 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
15081 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
15088 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
15095 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
15288 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
15716 #define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */
15723 #define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
15730 #define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
15737 #define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */
15744 #define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
15751 #define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
15758 #define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
15765 #define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
15772 #define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
15779 #define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
15786 #define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
15793 #define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
15800 #define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
15807 #define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
15814 #define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
15821 #define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
15828 #define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
15835 #define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
15842 #define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
15849 #define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
15856 #define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
15863 #define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
15870 #define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
15877 #define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
15884 #define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */
15894 #define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */
15901 #define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */
15908 #define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */
15915 #define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */
15922 #define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */
15929 #define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */
15936 #define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */
15943 #define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */
15950 #define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */
15957 #define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */
15964 #define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */
15971 #define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */
15978 #define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */
15985 #define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */
15992 #define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */
15999 #define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */
16006 #define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */
16013 #define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */
16020 #define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */
16027 #define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */
16034 #define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */
16041 #define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */
16048 #define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */
16055 #define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
16062 #define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */
16432 #define USBD_ENABLE_ENABLE_Disabled (0UL) /*!< USB peripheral is disabled */
16749 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
16759 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */