Lines Matching full:disabled

190 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
197 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
207 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
214 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
311 #define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled */
517 #define DPPIC_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
524 #define DPPIC_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
531 #define DPPIC_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
538 #define DPPIC_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
545 #define DPPIC_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
552 #define DPPIC_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
559 #define DPPIC_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
566 #define DPPIC_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
573 #define DPPIC_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
580 #define DPPIC_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
587 #define DPPIC_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
594 #define DPPIC_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
601 #define DPPIC_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
608 #define DPPIC_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
615 #define DPPIC_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
622 #define DPPIC_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
632 #define DPPIC_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
639 #define DPPIC_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
646 #define DPPIC_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
653 #define DPPIC_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
660 #define DPPIC_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
667 #define DPPIC_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
674 #define DPPIC_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
681 #define DPPIC_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
688 #define DPPIC_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
695 #define DPPIC_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
702 #define DPPIC_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
709 #define DPPIC_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
716 #define DPPIC_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
723 #define DPPIC_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
730 #define DPPIC_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
737 #define DPPIC_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
992 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
999 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1006 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1013 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1020 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1027 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1034 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1041 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1048 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1055 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1062 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1069 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1076 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1083 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1090 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1097 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1107 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1114 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1121 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1128 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1135 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1142 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1149 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1156 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1163 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1170 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1177 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1184 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1191 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1198 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1205 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1212 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1479 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
1486 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
1493 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
1500 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
1507 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
1514 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
1521 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
1528 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
1535 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
1545 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
1552 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
1559 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
1566 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
1573 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
1580 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
1587 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
1594 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
1601 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
1629 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired…
1776 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
1783 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
1790 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
1800 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
1807 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
1814 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
1842 #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to…
1851 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read fr…
1860 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not…
2127 #define IPC_INTENSET_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */
2134 #define IPC_INTENSET_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */
2141 #define IPC_INTENSET_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */
2148 #define IPC_INTENSET_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */
2155 #define IPC_INTENSET_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */
2162 #define IPC_INTENSET_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */
2169 #define IPC_INTENSET_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */
2176 #define IPC_INTENSET_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */
2186 #define IPC_INTENCLR_RECEIVE7_Disabled (0UL) /*!< Read: Disabled */
2193 #define IPC_INTENCLR_RECEIVE6_Disabled (0UL) /*!< Read: Disabled */
2200 #define IPC_INTENCLR_RECEIVE5_Disabled (0UL) /*!< Read: Disabled */
2207 #define IPC_INTENCLR_RECEIVE4_Disabled (0UL) /*!< Read: Disabled */
2214 #define IPC_INTENCLR_RECEIVE3_Disabled (0UL) /*!< Read: Disabled */
2221 #define IPC_INTENCLR_RECEIVE2_Disabled (0UL) /*!< Read: Disabled */
2228 #define IPC_INTENCLR_RECEIVE1_Disabled (0UL) /*!< Read: Disabled */
2235 #define IPC_INTENCLR_RECEIVE0_Disabled (0UL) /*!< Read: Disabled */
2465 #define KMU_INTENSET_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */
2472 #define KMU_INTENSET_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */
2479 #define KMU_INTENSET_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */
2489 #define KMU_INTENCLR_KEYSLOT_ERROR_Disabled (0UL) /*!< Read: Disabled */
2496 #define KMU_INTENCLR_KEYSLOT_REVOKED_Disabled (0UL) /*!< Read: Disabled */
2503 #define KMU_INTENCLR_KEYSLOT_PUSHED_Disabled (0UL) /*!< Read: Disabled */
4396 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
4570 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
4577 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
4584 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
4594 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
4601 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
4608 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
4857 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
4864 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
4871 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
4881 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
4888 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
4895 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
5221 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
5228 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
5235 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
5242 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
5249 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
5256 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
5263 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5273 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
5280 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
5287 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
5294 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
5301 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
5308 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
5315 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
5325 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
5382 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
5397 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is…
5468 #define REGULATORS_DCDCEN_DCDCEN_Disabled (0UL) /*!< DC/DC mode is disabled */
5631 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5638 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
5645 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
5652 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5659 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5666 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
5676 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5683 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
5690 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
5697 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5704 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5711 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
5760 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5767 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
5774 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
5781 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5788 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5795 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
5805 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
5812 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
5819 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
5826 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
5833 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
5840 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
6270 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
6277 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
6284 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
6291 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
6298 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
6305 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
6312 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
6319 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
6326 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
6333 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
6340 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
6347 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
6354 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
6361 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
6368 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
6375 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
6382 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6389 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
6396 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
6403 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
6410 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6417 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
6427 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
6434 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
6441 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
6448 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
6455 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
6462 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
6469 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
6476 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
6483 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
6490 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
6497 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
6504 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
6511 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
6518 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
6525 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
6532 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
6539 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6546 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
6553 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
6560 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
6567 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
6574 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
6636 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
6974 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
6981 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
6988 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6995 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7002 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7012 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
7019 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
7026 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
7033 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7040 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
7321 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
7328 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7335 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
7345 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
7352 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
7359 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
7626 #define SPU_INTENSET_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */
7633 #define SPU_INTENSET_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */
7640 #define SPU_INTENSET_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */
7650 #define SPU_INTENCLR_PERIPHACCERR_Disabled (0UL) /*!< Read: Disabled */
7657 #define SPU_INTENCLR_FLASHACCERR_Disabled (0UL) /*!< Read: Disabled */
7664 #define SPU_INTENCLR_RAMACCERR_Disabled (0UL) /*!< Read: Disabled */
8511 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
8518 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
8525 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8532 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8539 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8546 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8556 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
8563 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
8570 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
8577 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
8584 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
8591 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
8983 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
8990 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
8997 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9004 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9011 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
9018 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
9025 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9035 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
9042 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
9049 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9056 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9063 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
9070 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9077 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9515 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
9522 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
9529 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9536 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9543 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
9550 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9560 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
9567 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
9574 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9581 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
9588 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
9595 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9717 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
9723 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
10174 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10181 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10188 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10195 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
10202 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
10209 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10216 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
10223 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10230 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
10237 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
10244 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
10254 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
10261 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10268 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
10275 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
10282 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
10289 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10296 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
10303 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10310 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
10317 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
10324 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
10501 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
10807 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
10817 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */